公开(公告)号：US4992977A

公开(公告)日：1991-02-12

申请号：US173296

申请日：1988-03-25

申请人： Tsukasa Matoba ,  Takeshi Aikawa ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Mitsuyoshi Okamura

发明人： Tsukasa Matoba ,  Takeshi Aikawa ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Mitsuyoshi Okamura

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3812 ,  G06F12/0804 ,  G06F12/0848

摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

摘要翻译： 高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。 指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。 当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使 标签部分的有效标志。

公开(公告)号：US5021993A

公开(公告)日：1991-06-04

申请号：US175224

申请日：1988-03-30

申请人： Tsukasa Matoba ,  Takeshi Aikawa ,  Mitsuyoshi Okamura ,  Ken-ichi Maeda ,  Mitsuo Saito

发明人： Tsukasa Matoba ,  Takeshi Aikawa ,  Mitsuyoshi Okamura ,  Ken-ichi Maeda ,  Mitsuo Saito

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48 ,  G11C7/10

CPC分类号： G06F9/30189 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/4426 ,  G06F9/462 ,  G11C7/1006

摘要： Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

公开(公告)号：US4945510A

公开(公告)日：1990-07-31

申请号：US133737

申请日：1987-12-16

申请人： Ken-ichi Maeda ,  Mitsuo Saito ,  Takeshi Aikawa ,  Tsukasa Matoba ,  Mitsuyoshi Okamura

发明人： Ken-ichi Maeda ,  Mitsuo Saito ,  Takeshi Aikawa ,  Tsukasa Matoba ,  Mitsuyoshi Okamura

IPC分类号： G06F9/34 ,  G06F9/42 ,  G06F9/46

CPC分类号： G06F9/30116 ,  G06F9/4426 ,  G06F9/462

摘要： A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

公开(公告)号：US5717625A

公开(公告)日：1998-02-10

申请号：US784963

申请日：1997-01-16

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

CPC分类号： G11C8/08 ,  G11C11/4045

摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

公开(公告)号：US4876657A

公开(公告)日：1989-10-24

申请号：US81747

申请日：1987-08-05

申请人： Mitsuo Saito ,  Tsukasa Matoba ,  Toshio Okamoto

发明人： Mitsuo Saito ,  Tsukasa Matoba ,  Toshio Okamoto

IPC分类号： G06F3/033 ,  G06F3/048 ,  G06F3/153 ,  G09G5/00 ,  G09G5/02

CPC分类号： G09G5/022 ,  G06F3/033 ,  G06F3/04845 ,  G06F3/153

摘要： A presentation display apparatus including a data storage section for storing a plurality of explanative image data each having (R), (G) and (B) color image components, a data processing section for adding, to the explanative image data from the data storage section, function select image data different in color component from the explanative image data, an image memory for storing the image data of one screen image output from the data processing section, a listener's first display device for displaying the image data which is delivered from image memory and a speaker's second display device. The image data output from the image memory is supplied through a first color converter to the listener's display device and through a second color converter to the speaker's display device. In the first color converter, the explanative image data is alone directly delivered as conversion image data in spite of function select menu image data, so that only the explanative (R)/(G)/(B) image is displayed on the listener's display device. In the second converter, the (R)/(G)/(B) input data are directly output as conversion image data when the function select image data is "0" and otherwise converted to all "1" when the function select menu image is "1" so that the function select menu and (R)/(G)/(B) explanative image are overlappingly displayed on the second display device.

摘要翻译： 一种呈现显示装置，包括：数据存储部分，用于存储具有（R），（G）和（B）彩色图像分量的多个解释图像数据;数据处理部分，用于将来自数据存储器的解释图像数据 功能选择与解释图像数据不同的颜色分量的图像数据，用于存储从数据处理部分输出的一个屏幕图像的图像数据的图像存储器，用于显示从图像传送的图像数据的收听者的第一显示装置 存储器和扬声器的第二显示装置。 从图像存储器输出的图像数据通过第一颜色转换器提供给收听者的显示装​​置，并通过第二颜色转换器提供给扬声器的显示装置。 在第一颜色转换器中，尽管功能选择菜单图像数据，解释图像数据单独直接传送为转换图像数据，使得只有解释性（R）/（G）/（B）图像被显示在收听者的显示器上 设备。 在第二转换器中，当功能选择图像数据为“0”时，（R）/（G）/（B）输入数据直接作为转换图像数据输出，否则当功能选择菜单图像被转换为​​全部“1” 是“1”，使得功能选择菜单和（R）/（G）/（B）解释图像被重叠地显示在第二显示装置上。

公开(公告)号：US5561774A

公开(公告)日：1996-10-01

申请号：US291582

申请日：1994-08-16

申请人： Takeshi Aikawa ,  Mitsuo Saito ,  Kenji Minagawa ,  Kenji Takeda

发明人： Takeshi Aikawa ,  Mitsuo Saito ,  Kenji Minagawa ,  Kenji Takeda

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863 ,  G06F9/3885

摘要： A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.

摘要翻译： 一种具有陷波和失速控制功能的并行处理型处理器系统，其能够在不增加周期时间的情况下进行操作，从而可以防止系统中的时钟频率的降低。 在该系统中，处理器单元被控制，使得当在执行提供给处理器单元的至少一个指令的同时执行异常时，同时提供给处理器单元的所有指令的处理被中止。 此外，当不可能在执行提供给处理器单元的指令的同时拒绝发生异常的可能性时，同时提供给处理器单元的指令的处理被停止。

公开(公告)号：US5414822A

公开(公告)日：1995-05-09

申请号：US863181

申请日：1992-04-03

申请人： Mitsuo Saito ,  Takeshi Aikawa ,  Junji Mori

发明人： Mitsuo Saito ,  Takeshi Aikawa ,  Junji Mori

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3806 ,  G06F9/3844

摘要： The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.

摘要翻译： 该分支预测使用由适用于超标量处理器的关联存储器形成的分支预测表，而不会导致分支预测中的混淆。 分支预测使用用于登记条目的分支预测表，每个条目包括分支地址，分支目标地址和指示同时执行的指令组中的预测分支指令的位置的指示位置，或指示 每个条目在表的关联记忆中的位置。 通过使用实际分支目标地址和/或在当前取得的指令的实际执行中遇到的实际分支指令的实际指令位置来检查预测分支指令的正确性。 当预测分支指令不正确时，在下一个处理定时取出的指令无效，表中的条目被重写。

公开(公告)号：US5163127A

公开(公告)日：1992-11-10

申请号：US687772

申请日：1991-04-19

申请人： Nobuyuki Ikumi ,  Mitsuo Saito ,  Takeshi Aikawa ,  Masahide Ohhashi

发明人： Nobuyuki Ikumi ,  Mitsuo Saito ,  Takeshi Aikawa ,  Masahide Ohhashi

IPC分类号： G06T15/40 ,  G06T15/80

CPC分类号： G06T15/87

摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.

摘要翻译： 三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器 。 在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。 每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。

公开(公告)号：US4660181A

公开(公告)日：1987-04-21

申请号：US714396

申请日：1985-03-21

申请人： Mitsuo Saito ,  Takeshi Aikawa ,  Akio Mori

发明人： Mitsuo Saito ,  Takeshi Aikawa ,  Akio Mori

IPC分类号： G06F3/153 ,  G06F12/04 ,  G09G5/00 ,  G09G5/39 ,  G09G5/395 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12

CPC分类号： G11C8/00 ,  G06F12/04 ,  G11C7/00 ,  G11C7/1006 ,  G11C8/12

摘要： A memory system includes a memory which consists of a plurality of bit memory cells each capable of being independently accessible and of storing bit data in at least a first and a second different predetermined bit width access mode. A multiplexer and address decoder are provided together with a bit width register for producing first and second write control signals corresponding to the first and second access modes respectively for enabling writing within the independently accessible memory cells of data having respectively first and a different second bit width.

摘要翻译： 存储器系统包括存储器，该存储器由多个位存储器单元构成，每个存储器单元能独立存取，并且以至少第一和第二不同的预定位宽度访问模式存储位数据。 多路复用器和地址解码器与位宽寄存器一起提供，用于产生分别对应于第一和第二访问模式的第一和第二写入控制信号，以使得能够在可独立存取的存储单元内写入分别具有第一和不同的第二位宽的数据 。

公开(公告)号：US5377339A

公开(公告)日：1994-12-27

申请号：US191069

申请日：1994-02-03

申请人： Mitsuo Saito ,  Kenji Minagawa ,  Takeshi Aikawa

发明人： Mitsuo Saito ,  Kenji Minagawa ,  Takeshi Aikawa

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/382 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

摘要： A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructions and a corresponding decision result are stored in the cache memory. The decision process is performed for several groups of the plural instructions read out from the main memory to the cache memory in order. Then, the plural instructions are respectively assigned to a corresponding operation unit according to the decision result, and are subsequently executed by the corresponding operation unit. As a result of this arrangement, the repeated decision process for the plural instructions is not necessary when they are later read out from the cache memory to the operation unit.

摘要翻译： 当从主存储器向高速缓冲存储器读出指令时，用于同时执行多个指令的计算机决定多种指令的操作种类和同时执行的可能性。 多个指令和相应的判定结果存储在高速缓冲存储器中。 对从主存储器读出的多组指令的顺序执行到高速缓冲存储器的决定处理。 然后，根据判定结果将多个指令分别分配给对应的运算单元，并由随后的运算单元执行。 作为这种布置的结果，当它们稍后从高速缓冲存储器读出到操作单元时，不需要多个指令的重复确定处理。