公开(公告)号：US5717625A

公开(公告)日：1998-02-10

申请号：US784963

申请日：1997-01-16

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

CPC分类号： G11C8/08 ,  G11C11/4045

摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

公开(公告)号：US4992977A

公开(公告)日：1991-02-12

申请号：US173296

申请日：1988-03-25

申请人： Tsukasa Matoba ,  Takeshi Aikawa ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Mitsuyoshi Okamura

发明人： Tsukasa Matoba ,  Takeshi Aikawa ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Mitsuyoshi Okamura

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3812 ,  G06F12/0804 ,  G06F12/0848

摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

摘要翻译： 高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。 指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。 当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使 标签部分的有效标志。

公开(公告)号：US4945510A

公开(公告)日：1990-07-31

申请号：US133737

申请日：1987-12-16

申请人： Ken-ichi Maeda ,  Mitsuo Saito ,  Takeshi Aikawa ,  Tsukasa Matoba ,  Mitsuyoshi Okamura

发明人： Ken-ichi Maeda ,  Mitsuo Saito ,  Takeshi Aikawa ,  Tsukasa Matoba ,  Mitsuyoshi Okamura

IPC分类号： G06F9/34 ,  G06F9/42 ,  G06F9/46

CPC分类号： G06F9/30116 ,  G06F9/4426 ,  G06F9/462

摘要： A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

公开(公告)号：US5021993A

公开(公告)日：1991-06-04

申请号：US175224

申请日：1988-03-30

申请人： Tsukasa Matoba ,  Takeshi Aikawa ,  Mitsuyoshi Okamura ,  Ken-ichi Maeda ,  Mitsuo Saito

发明人： Tsukasa Matoba ,  Takeshi Aikawa ,  Mitsuyoshi Okamura ,  Ken-ichi Maeda ,  Mitsuo Saito

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48 ,  G11C7/10

CPC分类号： G06F9/30189 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/4426 ,  G06F9/462 ,  G11C7/1006

摘要： Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

公开(公告)号：US07654360B2

公开(公告)日：2010-02-02

申请号：US11520875

申请日：2006-09-14

申请人： Mitsuo Saito ,  Isamu Arai

发明人： Mitsuo Saito ,  Isamu Arai

IPC分类号： B62D15/02

CPC分类号： B62D5/04 ,  B62D1/16 ,  B62D1/20 ,  B62D5/0409 ,  B62K5/01 ,  B62K5/08

摘要： In a motor-driven steering apparatus structured such that a motor-driven steering assist unit is interposed between a steering shaft in a handle side and a wheel side steering member, and an input shaft connected to the steering shaft of the motor-driven steering assist unit and an output shaft connected to the wheel side steering member are coupled by a torsion bar and arranged on the same center axis, reference angle position marks are applied to portions existing at the same angle position around the same center axis of the input shaft and the output shaft, in a neutral steering state in which a steering force is not applied to the input shaft of the motor-driven steering assist unit.

摘要翻译： 在电机驱动的转向装置中，电机驱动的转向辅助单元被插入在手柄侧的转向轴与车轮侧的转向构件之间，以及连接到电动助力转向辅助的转向轴的输入轴 连接到车轮侧转向构件的单元和输出轴通过扭杆联接并且布置在相同的中心轴上，参考角位置标记被施加到围绕输入轴的相同中心轴线的相同角度位置处存在的部分， 所述输出轴处于不向所述电动助力转向辅助单元的输入轴施加转向力的中立转向状态。

公开(公告)号：US07540511B2

公开(公告)日：2009-06-02

申请号：US11900960

申请日：2007-09-14

申请人： Mitsuo Saito ,  Koichi Hata ,  Hideo Yanai

发明人： Mitsuo Saito ,  Koichi Hata ,  Hideo Yanai

IPC分类号： B62D7/22

CPC分类号： B62D5/0403 ,  B62D1/16 ,  B62D5/0409

摘要： In a support structure of a motor-driven steering assist apparatus interposed between an upper steering shaft in a steering wheel side and a lower steering shaft in a tire wheel side, a steering angle regulating means for limiting a maximum steering angle of the upper steering shaft is provided between the upper steering shaft and a vehicle body side and a steering angle regulating means for limiting a maximum steering angle of the lower steering shaft is provided between the lower steering shaft and the vehicle body side.

摘要翻译： 在设置在方向盘一侧的上转向轴和轮胎车轮侧的下转向轴之间的电动助力转向辅助装置的支撑结构中，限制上转向轴的最大转向角的转向角调节装置 设置在上转向轴和车体侧之间，并且在下转向轴和车体侧之间设置用于限制下转向轴的最大转向角的转向角调节装置。

公开(公告)号：US5561774A

公开(公告)日：1996-10-01

申请号：US291582

申请日：1994-08-16

申请人： Takeshi Aikawa ,  Mitsuo Saito ,  Kenji Minagawa ,  Kenji Takeda

发明人： Takeshi Aikawa ,  Mitsuo Saito ,  Kenji Minagawa ,  Kenji Takeda

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863 ,  G06F9/3885

摘要： A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.

摘要翻译： 一种具有陷波和失速控制功能的并行处理型处理器系统，其能够在不增加周期时间的情况下进行操作，从而可以防止系统中的时钟频率的降低。 在该系统中，处理器单元被控制，使得当在执行提供给处理器单元的至少一个指令的同时执行异常时，同时提供给处理器单元的所有指令的处理被中止。 此外，当不可能在执行提供给处理器单元的指令的同时拒绝发生异常的可能性时，同时提供给处理器单元的指令的处理被停止。

公开(公告)号：US5414822A

公开(公告)日：1995-05-09

申请号：US863181

申请日：1992-04-03

申请人： Mitsuo Saito ,  Takeshi Aikawa ,  Junji Mori

发明人： Mitsuo Saito ,  Takeshi Aikawa ,  Junji Mori

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3806 ,  G06F9/3844

摘要： The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.

摘要翻译： 该分支预测使用由适用于超标量处理器的关联存储器形成的分支预测表，而不会导致分支预测中的混淆。 分支预测使用用于登记条目的分支预测表，每个条目包括分支地址，分支目标地址和指示同时执行的指令组中的预测分支指令的位置的指示位置，或指示 每个条目在表的关联记忆中的位置。 通过使用实际分支目标地址和/或在当前取得的指令的实际执行中遇到的实际分支指令的实际指令位置来检查预测分支指令的正确性。 当预测分支指令不正确时，在下一个处理定时取出的指令无效，表中的条目被重写。

公开(公告)号：US5163127A

公开(公告)日：1992-11-10

申请号：US687772

申请日：1991-04-19

申请人： Nobuyuki Ikumi ,  Mitsuo Saito ,  Takeshi Aikawa ,  Masahide Ohhashi

发明人： Nobuyuki Ikumi ,  Mitsuo Saito ,  Takeshi Aikawa ,  Masahide Ohhashi

IPC分类号： G06T15/40 ,  G06T15/80

CPC分类号： G06T15/87

摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.

摘要翻译： 三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器 。 在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。 每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。

公开(公告)号：US5067593A

公开(公告)日：1991-11-26

申请号：US438014

申请日：1989-11-20

申请人： Masakatsu Tanaka ,  Masanobu Itoh ,  Noboru Arabori ,  Toshihiko Nara ,  Tastuhiko Takahashi ,  Katutaro Masuda ,  Mitsuo Saito

发明人： Masakatsu Tanaka ,  Masanobu Itoh ,  Noboru Arabori ,  Toshihiko Nara ,  Tastuhiko Takahashi ,  Katutaro Masuda ,  Mitsuo Saito

IPC分类号： B66B11/08 ,  B66B1/28 ,  B66B5/04 ,  B66D5/14 ,  B66D5/30 ,  F16D55/00 ,  F16D55/28 ,  F16D59/02 ,  F16D65/14 ,  F16D65/18 ,  F16D69/04

CPC分类号： F16D55/28 ,  B66B1/28 ,  B66B5/04 ,  B66D5/14 ,  B66D5/30 ,  F16D59/02 ,  F16D2055/0058 ,  F16D2065/383 ,  F16D2121/22 ,  Y10T477/393

摘要： A braking device for an elevator winding machine generates a braking force by contacting a rotary body driven by a rotary shaft of the winding machine with a brake section supported through the intermediary of an elastic body. The elastic body has a nonlinear elastic characteristic so that a starting shock to the passengers in the elevator car is prevented and the braking torque detecting accuracy is improved.

摘要翻译： 用于电梯绕线机的制动装置通过使由绕线机的旋转轴驱动的旋转体与通过弹性体的中间支撑的制动部分接触而产生制动力。 该弹性体具有非线性的弹性特性，能够防止对电梯轿厢的乘客的起动冲击，提高制动转矩检测精度。