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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5717625A

    公开(公告)日：1998-02-10

    申请号：US784963

    申请日：1997-01-16

    申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

    发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

    IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

    CPC分类号： G11C8/08 ,  G11C11/4045

    摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

    摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

    Semiconductor memory device using dynamic type memory cells
    4.
    发明授权
    Semiconductor memory device using dynamic type memory cells 失效
    半导体存储器件采用动态型存储单元

    公开(公告)号：US5661678A

    公开(公告)日：1997-08-26

    申请号：US570966

    申请日：1995-12-12

    申请人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

    发明人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

    IPC分类号： H01L21/8242 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10829

    摘要： A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.

    摘要翻译： 半导体存储器件包括存储单元阵列，其包括以矩阵形式布置的NAND型存储单元单元，并且具有串联连接的多个动态型存储单元，多个字线，布置在存储单元阵列内的多个位线， 多个位线包括彼此相邻布置或位于其中的至少一个位线之间布置的位线对以及设置在多个位线对中的每一个中的折叠位线类型的多个读出放大器 其中存储单元被提供在与位线和字线的交点对应的位置中，并且互补数据被写入连接到多个位线对和一个字线中的每一个的两个存储器单元，并且两个存储器 单元存储一位数据。

    Semiconductor memory device for suppressing noises occurring on bit and word lines
    5.
    发明授权
    Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
    用于抑制位和字线上发生的噪声的半导体存储器件

    公开(公告)号：US5418750A

    公开(公告)日：1995-05-23

    申请号：US200107

    申请日：1994-02-22

    申请人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

    发明人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

    IPC分类号： G11C11/407 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

    摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.

    摘要翻译： 半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取 连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于 选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管 第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组 第一位线组以相反的方向规则地布置。

    Semiconductor memory device with reduced read time and power consumption
    6.
    发明授权
    Semiconductor memory device with reduced read time and power consumption 失效
    半导体存储器件具有减少的读取时间和功耗

    公开(公告)号：US5654912A

    公开(公告)日：1997-08-05

    申请号：US568500

    申请日：1995-12-07

    申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

    发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/103

    摘要： A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

    摘要翻译： 半导体存储器件包括存储器阵列，其中字线由单个解码器驱动，或者由存储器阵列或存储器阵列存储单元单元中的由相同行地址操作的多个解码器驱动的多个存储器阵列驱动，其中， 多个存储单元以阵列的形式串联连接，多个读出放大器阵列通过布置多个读出放大器而构成，每个读出放大器分别设置用于一对位线或多对位线以读出 来自存储单元阵列的存储单元的数据，读出放大器阵列被划分为多个块，以及对应于一个存储单元阵列的块，具有多个寄存器的寄存器阵列，用于存储由多个块读出的数据 读出放大器，寄存器阵列被分成多个块，以及对应于读出放大器块和一个存储单元阵列的块，以及控制ci 用于独立控制读出放大器阵列和寄存器阵列的块，并独立地从块中的寄存器读出数据。

    Semiconductor memory device including a plurality of dynamic memory cells connected in series
    7.
    发明授权
    Semiconductor memory device including a plurality of dynamic memory cells connected in series 失效
    半导体存储器件包括串联连接的多个动态存储单元

    公开(公告)号：US5831928A

    公开(公告)日：1998-11-03

    申请号：US744455

    申请日：1996-11-07

    申请人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

    发明人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

    CPC分类号： G11C7/10 ,  G11C11/4096

    摘要： A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.

    摘要翻译： 半导体器件包括具有以矩阵形式布置的存储单元的存储单元阵列，用于向存储单元传送信息的多个位线以及与位线交叉的多条字线以便在存储单元之间进行选择， 用于放大读取到位线上的数据的读出放大器，用于将由读出放大器放大的数据传送到单元阵列外部的多条数据线，多条数据线包括第一和第二布线层，多列列选择 用于控制多个数据线和多个读出放大器的连接的电路以及连接到多个列选择电路的多个控制信号线，所述多个控制线包括第三和第四布线层。

    Semiconductor memory
    8.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5463577A

    公开(公告)日：1995-10-31

    申请号：US365104

    申请日：1994-12-28

    申请人： Yukihito Oowaki ,  Takehiro Hasegawa

    发明人： Yukihito Oowaki ,  Takehiro Hasegawa

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  G11C11/407 ,  G11C11/24

    CPC分类号： G11C8/12 ,  G11C8/14

    摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.

    摘要翻译： 提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。 存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容 访问。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5038191A

    公开(公告)日：1991-08-06

    申请号：US486842

    申请日：1990-03-01

    申请人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/404 ,  G11C11/411 ,  G11C11/412 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/102 ,  H01L29/73 ,  H01L29/732

    CPC分类号： G11C11/4113 ,  G11C11/404 ,  G11C11/412

    摘要： A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.

    摘要翻译： 半导体存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，排列成列的多个字线和排成行的多个位线。 每个存储单元包括双极晶体管，其中控制集电极 - 发射极电压，使得基极电流变化的极性根据基极 - 发射极电压的增加而改变，并且开关元件设置在基极 双极晶体管和相关联的位线，并且可由相关联的字线控制。 提供一种开关电路，用于在第二状态下将集电极电压施加到双极晶体管的集电极，在第二状态下，相关联的一个存储单元保持数据而不是相关联的存储单元可访问用于数据读取和数据的第二状态 写作。