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公开(公告)号：US07623580B2
公开(公告)日：2009-11-24
申请号：US10882083
申请日：2004-06-29
申请人： Kendal McNaught-Davis Hess , Manjit S. Gill , Donald Brian Eidson , Chi-Ping Nee , Mats Lindstrom , Abraham Krieger , Fred Harris
发明人： Kendal McNaught-Davis Hess , Manjit S. Gill , Donald Brian Eidson , Chi-Ping Nee , Mats Lindstrom , Abraham Krieger , Fred Harris
IPC分类号： H04K1/10
CPC分类号： H04H20/28 , H04H40/18 , H04H40/90 , H04N5/4401 , H04N21/42607 , H04N21/43615 , H04N21/4382 , H04N21/4385 , H04N21/44209
摘要： A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.
摘要翻译： 一种用于接收具有多个载波信号的组合信号的同时多信道接收机（“SMCR”），其中多个载波信号中的每个载波信号对应于频率信道，并且作为响应，同时产生多个输出数据流 信号。 SMCR可以包括能够接收组合信号的下变频器前端，多个数字信号处理器，其中多个数字信号处理器中的每个数字信号处理器能够产生多个数字信号处理器的输出数据流信号 输出数据流信号，以及与下变频器前端和多个数字信号处理器进行信号通信的多频带滤波器。
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2.发明授权Power amplifier operated as an envelope digital to analog converter with digital pre-distortion 有权功率放大器作为数字预失真的封装数模转换器公开(公告)号：US06255906B1
公开(公告)日：2001-07-03
申请号：US09410216
申请日：1999-09-30
IPC分类号： H03F368
CPC分类号： H03M1/74 , H03F1/0277 , H03F1/3241 , H03F3/602 , H03F2201/3233
摘要： A power amplifier that amplifies an electrical signal that is passed through a power amplification array. The power amplifier is employed in various applications including cellular telephones, radio frequency signal transmission, and other electrical signal applications requiring power amplification. The power amplifier contains a number of power amplifiers arranged in a power amplifier array. To reproduce a particular envelope profile, a selected number of the power amplifiers of the power amplifier array is switched ON, whereas another selected number of the power amplifiers of the power amplifier array are switched OFF. All elements are fed with an RF signal containing phase information as well. The amplified, output signal provided after the power amplifier array is fed to an antenna for signal transmission. Impedance matching circuitry is employed between the power amplifier array and the antenna to provide efficiency for those applications having low power budgets or seeking to operate with extremely high efficiency. The present invention provides a solution that is extremely energy efficient, making it ideally suited for applications having low available power budgets such as battery operated devices such as cellular telephones. From one perspective, the power amplifier array is operated as if it were a digital device. For example, each of the individual power amplifiers of the power amplifier array is either switched ON or switched OFF, as described above, and a selected number of the power amplifiers provides the desired level for the specific application.
摘要翻译： 放大通过功率放大阵列的电信号的功率放大器。 功率放大器用于各种应用，包括蜂窝电话，射频信号传输以及需要功率放大的其他电信号应用。 功率放大器包含多个布置在功率放大器阵列中的功率放大器。 为了再现特定的包络轮廓，所选数量的功率放大器阵列的功率放大器被接通，而功率放大器阵列的另一选定数量的功率放大器被切换为OFF。 所有元件也被馈送包含相位信息的RF信号。 在功率放大器阵列之后提供的放大的输出信号被馈送到天线进行信号传输。 在功率放大器阵列和天线之间采用阻抗匹配电路，以为具有低功率预算或寻求以非常高的效率运行的那些应用提供效率。 本发明提供了一种非常节能的解决方案，使其非常适用于具有低可用功率预算的应用，例如诸如蜂窝电话的电池供电装置。 从一个角度来看，功率放大器阵列就像数字设备一样被操作。 例如，如上所述，功率放大器阵列的各个功率放大器的每个都被切换为接通或关断，并且选定数量的功率放大器为特定应用提供期望的电平。
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3.发明授权Iterative decoder employing multiple external code error checks to lower the error floor 有权迭代解码器采用多个外部代码错误检查来降低错误的底数公开(公告)号：US07310768B2
公开(公告)日：2007-12-18
申请号：US10892738
申请日：2004-07-16
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M13/09 , H03M13/15 , H03M13/2936 , H03M13/2948 , H03M13/2972 , H03M13/3776 , H03M13/3994 , H04L1/0054 , H04L1/0061 , H04L1/0065 , H04L1/0066
摘要： Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.
摘要翻译： 迭代解码器采用多个外部码错误检查来降低错误帧和/或提高解码性能。 有时通过循环冗余校验（CRC）或Reed Solomon（RS）代码进行数据块冗余，可实现增强的迭代解码性能。 在最终迭代之前的中间迭代期间，可以实现改进的解码性能。 一个正确解码的CRC块，指示解码的段是高度确定的正确的，为该段中的位分配非常高的置信度水平，并将其反馈给内部和/或外部解码器（适当时进行交织），以便 改进的迭代解码。 高置信位可能散布在整个内部解码帧中，以影响后续迭代中的其他位决策。 Turbo解码器通常在BER高的区域相对较好地工作; 本发明改进了在较低BER下的迭代解码器操作，降低了常规turbo解码器有时成问题的“BER地面”。
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4.发明授权Iterative decoder employing multiple external code error checks to lower the error floor 有权迭代解码器采用多个外部代码错误检查来降低错误的底数公开(公告)号：US07568147B2
公开(公告)日：2009-07-28
申请号：US11944320
申请日：2007-11-21
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M13/09 , H03M13/15 , H03M13/2936 , H03M13/2948 , H03M13/2972 , H03M13/3776 , H03M13/3994 , H04L1/0054 , H04L1/0061 , H04L1/0065 , H04L1/0066
摘要： Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.
摘要翻译： 迭代解码器采用多个外部码错误检查来降低错误帧和/或提高解码性能。 有时通过循环冗余校验（CRC）或Reed Solomon（RS）代码进行数据块冗余，可实现增强的迭代解码性能。 在最终迭代之前的中间迭代期间，可以实现改进的解码性能。 一个正确解码的CRC块，指示解码的段是高度确定的正确的，为该段中的位分配非常高的置信度水平，并将其反馈给内部和/或外部解码器（适当时进行交织），以便 改进的迭代解码。 高置信位可能散布在整个内部解码帧中，以影响后续迭代中的其他位决策。 Turbo解码器通常在BER高的区域相对较好地工作; 本发明改进了在较低BER下的迭代解码器操作，降低了常规turbo解码器有时成问题的“BER地面”。
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5.发明授权Symbol reliability determination and symbol pre-selection based on reliability criteria 有权基于可靠性标准的符号可靠性确定和符号预选公开(公告)号：US07231005B2
公开(公告)日：2007-06-12
申请号：US10368017
申请日：2003-02-14
CPC分类号： H04L1/0054 , H04L1/0055 , H04L25/025 , H04L25/067 , H04L2025/03598
摘要： A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.
摘要翻译： 公开了一种用于处理包括接收符号数据的解调数据的方法和装置。 解码器用于计算估计符号和相应的可靠性度量。 可靠性度量被转化为可靠性权重。 可选地，计算与接收的符号数据和估计的符号之间的差有关的残差。 产生输出数据，包括以下任意组合：估计符号，可靠性权重，残差和接收到的符号数据。 可以通过可靠度度量对残差进行加权，并由解调或误差补偿回路使用，以瞬时减少或增加这些回路的带宽。
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公开(公告)号：US07310369B1
公开(公告)日：2007-12-18
申请号：US09870926
申请日：2001-05-30
CPC分类号： H04L1/20 , H04B17/26 , H04B17/336 , H04L1/0054 , H04L1/0055
摘要： A method for estimating an SNR-related parameter, such as ES/N0, from one or more symbols. The number of symbols within a predetermined number of symbols that fall within one or more collection areas is counted. The count is then associated with a value of the SNR-related parameter. This association may be performed through one or more lookup tables. In one application, a scaling factor is derived from the count. The scaling factor may be used to scale symbols before they are quantized and inputted into a trellis decoder such as a log-MAP decoder.
摘要翻译： 一种用于从一个或多个符号估计SNR相关参数的方法，例如E / S / N 0 0。 计数落入一个或多个收集区域内的预定数量的符号内的符号数。 然后计数与SNR相关参数的值相关联。 该关联可以通过一个或多个查找表来执行。 在一个应用中，从计数导出缩放因子。 比例因子可以在量化之前对符号进行缩放并输入到诸如log-MAP解码器的网格解码器中。
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公开(公告)号：US07103831B1
公开(公告)日：2006-09-05
申请号：US10350303
申请日：2003-01-22
IPC分类号： H03M13/00
CPC分类号： H03M13/4169 , H03M13/2936 , H03M13/4138
摘要： A method and system are described for assigning reliability metrics to error correction coded bits or symbols that are decoded. Survivor and non-survivor paths through a portion of a trellis representation within a sliding window are determined and recorded. Primary and non-primary traceback paths through a portion of the trellis representation are determined from the recorded data. If the primary and non-primary traceback paths diverge at a release point, a reliability metric is assigned to the bit or symbol estimate corresponding to the release point. This metric is derived from the difference between the path metrics of the primary and non-primary traceback paths. Alternately, if the two paths diverge through all or a portion of a release zone, a reliability metric is assigned to the block of bit or symbol estimates corresponding to the portion or more of the release zone where the two paths diverge from one another. Again, this metric is derived from the difference between the path metrics of the primary and non-primary traceback paths.
摘要翻译： 描述了用于将可靠性度量分配给被解码的纠错编码比特或符号的方法和系统。 确定并记录通过滑动窗口内的网格表示的一部分的幸存者和非幸存者路径。 从记录的数据确定通过网格表示的一部分的主要和非主要回溯路径。 如果主要和非主要回溯路径在释放点发散，则将可靠性度量分配给与释放点相对应的位或符号估计。 该度量来源于主要和非主要回溯路径的路径度量之间的差异。 或者，如果两个路径分开通过释放区域的全部或一部分，则可靠性度量被分配给对应于两个路径彼此分开的释放区域的部分或更多个的位或符号估计块。 同样，该度量来源于主要和非主要回溯路径的路径度量之间的差异。
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8.发明授权Method and apparatus for decoding of a serially concatenated block and convolutional code 有权用于对串行级联块和卷积码进行解码的方法和装置公开(公告)号：US06606724B1
公开(公告)日：2003-08-12
申请号：US09492962
申请日：2000-01-28
IPC分类号： H03M1300
CPC分类号： H03M13/2972 , H03M13/09 , H03M13/15 , H03M13/2936 , H03M13/2948 , H03M13/3776 , H03M13/3994
摘要： A decoder having a first decoder providing first decoded data. A deinterleaver is included for deinterleaving the first decoded data. A second decoder provides second decoded data based on the deinterleaved first decoded data. The second decoder provides at least one decode status signal indicative of second decoder operations. A pipeline decoder unit is included that is coupled to the second decoder. The pipeline decoder unit includes an encoder that receives the second decoded data and provides forced decision data, a multiplexer, and a third decoder that provides pipelined decoded data. The multiplexer is responsive to the at least one decode status signal to selectively constrain the pipelined decoded data to be at least partially dependent on the forced decision data.
摘要翻译： 一种解码器，具有提供第一解码数据的第一解码器。 包含解交织器用于对第一解码数据进行解交织。 第二解码器基于去交织的第一解码数据提供第二解码数据。 第二解码器提供指示第二解码器操作的至少一个解码状态信号。 包括耦合到第二解码器的流水线解码器单元。 管线解码器单元包括接收第二解码数据并提供强制判定数据的编码器，多路复用器和提供流水线解码数据的第三解码器。 复用器响应于至少一个解码状态信号，以选择性地约束流水线解码的数据至少部分地取决于强制判定数据。
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9.发明授权Efficient communication system for reliable frame transmission over broad SNR ranges 失效高效的通信系统，用于在宽SNR范围内进行可靠的帧传输公开(公告)号：US07336683B1
公开(公告)日：2008-02-26
申请号：US10464361
申请日：2003-06-17
IPC分类号： H04J3/00
CPC分类号： H04B7/18595 , H04L1/0089
摘要： An exemplary satellite communication system comprises a service provider unit communicably coupled to a number of subscriber units via satellite transmission. The service provider unit includes an encoder configured to encode source data into a serial transmit sequence, and is further capable of supporting at least two modes of operation. The serial transmit sequence includes a first unique word identifying a first mode of operation, and is followed by a first payload packet having a first number of channel symbols corresponding to a source packet encoded in accordance with the first mode of operation identified by the first unique word. The first payload packet is encapsulated by two unique words and the time interval between the two unique words is used to determine the first mode of operation identified by the first unique word.
摘要翻译： 示例性卫星通信系统包括通过卫星传输可通信地耦合到多个用户单元的服务提供商单元。 服务提供商单元包括被配置为将源数据编码为串行发送序列的编码器，并且还能够支持至少两种操作模式。 串行发送序列包括识别第一操作模式的第一唯一字，并且后面是第一有效载荷分组，其具有对应于根据由第一唯一的第一唯一标识的第一操作模式编码的源分组的第一数量的信道符号 字。 第一个有效载荷包被两个唯一字封装，并且两个唯一字之间的时间间隔用于确定由第一个唯一字识别的第一操作模式。
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公开(公告)号：US06856656B2
公开(公告)日：2005-02-15
申请号：US09729652
申请日：2000-12-04
CPC分类号： H04L1/005 , H04L1/0066 , H04L27/22 , H04L2027/003 , H04L2027/0055 , H04L2027/0067
摘要： An iterative system for performing carrier phase tracking of symbols using a serial turbo decoder. Estimates of a buffered block of symbols are provided by a serial turbo decoder. Optionally, reliability metrics for the estimates are provided as well. Responsive to this information, a tracking loop module determines derotation phases for each of the symbols in the buffer. A symbol derotator derotates each of the buffered symbols in the block by its corresponding derotation phase. The derotated symbols are stored back in the buffer. The process may repeat itself for a prescribed number of iterations, after which the serial turbo decoder provides estimates of the underlying source bits.
摘要翻译： 用于使用串行turbo解码器执行符号的载波相位跟踪的迭代系统。 缓冲符号块的估计由串行turbo解码器提供。 可选地，也提供估计的可靠性度量。 响应于该信息，跟踪循环模块确定缓冲器中每个符号的解旋相位。 符号解旋器通过其对应的解旋阶段来解除块中的每个缓冲符号。 被解码的符号被存储在缓冲区中。 该过程可以重复其规定次数的迭代，之后串行turbo解码器提供基础源比特的估计。
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