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公开(公告)号：US20050164442A1
公开(公告)日：2005-07-28
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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公开(公告)号：US07282411B2
公开(公告)日：2007-10-16
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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3.发明授权公开(公告)号：US07303951B2
公开(公告)日：2007-12-04
申请号：US11028867
申请日：2005-01-05
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/823878
摘要： A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
摘要翻译： 一种制造半导体器件的方法，该半导体器件用于防止在形成元件隔离沟槽的步骤中在沟槽内部引起的针状突起的栅电极的电介质击穿，其中包括在氮化硅膜上形成氧化硅膜作为蚀刻掩模 形成元件隔离沟槽，然后用氢氟酸蚀刻溶液清洗衬底的表面，以在通过使用提供的光致抗蚀剂膜作为掩模对图案化氮化硅膜的步骤之前提取沉积在氧化硅膜表面上的障碍物 在其下面有防反射膜。
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公开(公告)号：US20050153521A1
公开(公告)日：2005-07-14
申请号：US11028867
申请日：2005-01-05
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/823878
摘要： A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
摘要翻译： 一种制造半导体器件的方法，该半导体器件用于防止在形成元件隔离沟槽的步骤中在沟槽内部引起的针状突起的栅电极的电介质击穿，其中包括在氮化硅膜上形成氧化硅膜作为蚀刻掩模 形成元件隔离沟槽，然后用氢氟酸蚀刻溶液清洗衬底的表面，以在通过使用提供的光致抗蚀剂膜作为掩模对图案化氮化硅膜的步骤之前提取沉积在氧化硅膜表面上的障碍物 在其下面有防反射膜。
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公开(公告)号：US07180788B2
公开(公告)日：2007-02-20
申请号：US11030152
申请日：2005-01-07
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/24 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.
摘要翻译： 非易失性半导体存储器件通过减少直接外围电路的占用面积来提供更高的集成度，其中AND型闪速存储器的存储单元包括选择栅极，浮动栅极，用作字的控制栅极 线，以及用作局部位线的n型半导体区域（源极，漏极）。 在存储器垫中彼此相邻的一对局部位线在存储器衬垫的列的方向上的一端与一个全局位线连接，并且由一个增强型MOS晶体管和一个增强型MOS晶体管形成的选择MOS晶体管 耗尽型MOS晶体管; 与每对本地位线串联连接。 通过打开/关闭选择MOS晶体管来选择一个本地位线。
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公开(公告)号：US20050162885A1
公开(公告)日：2005-07-28
申请号：US11030152
申请日：2005-01-07
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C16/24 , H01L21/8239 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/24 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistors is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.
摘要翻译： 非易失性半导体存储器件通过减少直接外围电路的占用面积来提供更高的集成度，其中AND型闪速存储器的存储单元包括选择栅极，浮动栅极，用作字的控制栅极 线，以及用作局部位线的n型半导体区域（源极，漏极）。 在存储器垫中彼此相邻的一对局部位线在存储器衬垫的列的方向上的一端与一个全局位线连接，并且由一个增强型MOS晶体管和一个增强型MOS晶体管形成的选择MOS晶体管 耗尽型MOS晶体管与该对局部位线中的每一个串联连接。 通过打开/关闭选择MOS晶体管来选择一个本地位线。
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公开(公告)号：US20080293230A1
公开(公告)日：2008-11-27
申请号：US12183919
申请日：2008-07-31
申请人： Naohiro HOSODA , Kenji Kanamitsu
发明人： Naohiro HOSODA , Kenji Kanamitsu
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.
摘要翻译： 在半导体器件中的最上层三层布线上布置富硅氧化物（SRO）膜。 然后，对位于第三级布线上的氧化硅膜和氮化硅膜进行干蚀刻以暴露第三级布线的一部分，从而形成接合焊盘并在保险丝上形成开口。 在该过程中，SRO膜用作蚀刻停止层。 这优化了位于保险丝上的电介质膜的厚度。
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公开(公告)号：US20050151259A1
公开(公告)日：2005-07-14
申请号：US11028296
申请日：2005-01-04
申请人： Naohiro Hosoda , Kenji Kanamitsu
发明人： Naohiro Hosoda , Kenji Kanamitsu
IPC分类号： H01L23/522 , H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/525 , H01L23/532
CPC分类号： H01L23/5258 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.
摘要翻译： 在半导体器件中的最上层三层布线上布置富硅氧化物（SRO）膜。 然后，对位于第三级布线上的氧化硅膜和氮化硅膜进行干蚀刻以暴露第三级布线的一部分，从而形成接合焊盘并在保险丝上形成开口。 在该过程中，SRO膜用作蚀刻停止层。 这优化了位于保险丝上的电介质膜的厚度。
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公开(公告)号：US20070034935A1
公开(公告)日：2007-02-15
申请号：US11583092
申请日：2006-10-19
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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公开(公告)号：US07126184B2
公开(公告)日：2006-10-24
申请号：US11147310
申请日：2005-06-08
IPC分类号： H01L29/76 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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