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公开(公告)号：US20070034935A1
公开(公告)日：2007-02-15
申请号：US11583092
申请日：2006-10-19
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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公开(公告)号：US07126184B2
公开(公告)日：2006-10-24
申请号：US11147310
申请日：2005-06-08
IPC分类号： H01L29/76 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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公开(公告)号：US20050269623A1
公开(公告)日：2005-12-08
申请号：US11147310
申请日：2005-06-08
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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公开(公告)号：US07358129B2
公开(公告)日：2008-04-15
申请号：US11583092
申请日：2006-10-19
IPC分类号： H01L21/8238 , H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译： 促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。 闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有 氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖 氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。
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公开(公告)号：US07180788B2
公开(公告)日：2007-02-20
申请号：US11030152
申请日：2005-01-07
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/24 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.
摘要翻译： 非易失性半导体存储器件通过减少直接外围电路的占用面积来提供更高的集成度，其中AND型闪速存储器的存储单元包括选择栅极，浮动栅极，用作字的控制栅极 线，以及用作局部位线的n型半导体区域（源极，漏极）。 在存储器垫中彼此相邻的一对局部位线在存储器衬垫的列的方向上的一端与一个全局位线连接，并且由一个增强型MOS晶体管和一个增强型MOS晶体管形成的选择MOS晶体管 耗尽型MOS晶体管; 与每对本地位线串联连接。 通过打开/关闭选择MOS晶体管来选择一个本地位线。
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公开(公告)号：US20050162885A1
公开(公告)日：2005-07-28
申请号：US11030152
申请日：2005-01-07
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C16/24 , H01L21/8239 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/24 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistors is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.
摘要翻译： 非易失性半导体存储器件通过减少直接外围电路的占用面积来提供更高的集成度，其中AND型闪速存储器的存储单元包括选择栅极，浮动栅极，用作字的控制栅极 线，以及用作局部位线的n型半导体区域（源极，漏极）。 在存储器垫中彼此相邻的一对局部位线在存储器衬垫的列的方向上的一端与一个全局位线连接，并且由一个增强型MOS晶体管和一个增强型MOS晶体管形成的选择MOS晶体管 耗尽型MOS晶体管与该对局部位线中的每一个串联连接。 通过打开/关闭选择MOS晶体管来选择一个本地位线。
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公开(公告)号：US20050164442A1
公开(公告)日：2005-07-28
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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公开(公告)号：US07282411B2
公开(公告)日：2007-10-16
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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9.发明授权公开(公告)号：US06544839B1
公开(公告)日：2003-04-08
申请号：US09473297
申请日：1999-12-28
IPC分类号： H01L218242
CPC分类号： H01L21/823878 , H01L21/28061 , H01L21/76232 , H01L21/823481 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L29/4941 , H01L29/6659
摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
摘要翻译： 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。
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10.发明申请公开(公告)号：US20060022259A1
公开(公告)日：2006-02-02
申请号：US11239338
申请日：2005-09-30
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11546 , H01L29/42324
摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.
摘要翻译： 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。
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