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公开(公告)号：US20050164442A1
公开(公告)日：2005-07-28
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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公开(公告)号：US07282411B2
公开(公告)日：2007-10-16
申请号：US11036023
申请日：2005-01-18
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate, insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译： 一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和 选择栅极）。 在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。 此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜， 已形成n型半导体区域，形成较厚。
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3.发明授权公开(公告)号：US07303951B2
公开(公告)日：2007-12-04
申请号：US11028867
申请日：2005-01-05
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/823878
摘要： A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
摘要翻译： 一种制造半导体器件的方法，该半导体器件用于防止在形成元件隔离沟槽的步骤中在沟槽内部引起的针状突起的栅电极的电介质击穿，其中包括在氮化硅膜上形成氧化硅膜作为蚀刻掩模 形成元件隔离沟槽，然后用氢氟酸蚀刻溶液清洗衬底的表面，以在通过使用提供的光致抗蚀剂膜作为掩模对图案化氮化硅膜的步骤之前提取沉积在氧化硅膜表面上的障碍物 在其下面有防反射膜。
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公开(公告)号：US20050153521A1
公开(公告)日：2005-07-14
申请号：US11028867
申请日：2005-01-05
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/823878
摘要： A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
摘要翻译： 一种制造半导体器件的方法，该半导体器件用于防止在形成元件隔离沟槽的步骤中在沟槽内部引起的针状突起的栅电极的电介质击穿，其中包括在氮化硅膜上形成氧化硅膜作为蚀刻掩模 形成元件隔离沟槽，然后用氢氟酸蚀刻溶液清洗衬底的表面，以在通过使用提供的光致抗蚀剂膜作为掩模对图案化氮化硅膜的步骤之前提取沉积在氧化硅膜表面上的障碍物 在其下面有防反射膜。
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公开(公告)号：US20050151259A1
公开(公告)日：2005-07-14
申请号：US11028296
申请日：2005-01-04
申请人： Naohiro Hosoda , Kenji Kanamitsu
发明人： Naohiro Hosoda , Kenji Kanamitsu
IPC分类号： H01L23/522 , H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/525 , H01L23/532
CPC分类号： H01L23/5258 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.
摘要翻译： 在半导体器件中的最上层三层布线上布置富硅氧化物（SRO）膜。 然后，对位于第三级布线上的氧化硅膜和氮化硅膜进行干蚀刻以暴露第三级布线的一部分，从而形成接合焊盘并在保险丝上形成开口。 在该过程中，SRO膜用作蚀刻停止层。 这优化了位于保险丝上的电介质膜的厚度。
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公开(公告)号：US07419869B2
公开(公告)日：2008-09-02
申请号：US11350117
申请日：2006-02-09
申请人： Naohiro Hosoda , Tetsuo Adachi
发明人： Naohiro Hosoda , Tetsuo Adachi
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546
摘要： Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.
摘要翻译： 提供一种半导体器件的制造方法，其具有以下步骤：以半导体衬底的形式层叠绝缘膜，用于形成浮栅电极的导体膜和另一绝缘膜，形成多个层叠图案 在所述多个层叠图案的侧表面上形成侧壁，通过干蚀刻去除任何两个相邻层叠图案之间的半导体衬底的损伤层，在两个相邻层叠图案之间的半导体衬底上形成绝缘膜，并形成多个 的辅助栅电极在两个相邻层叠图案之间的绝缘膜上自对准。 根据本发明，具有闪速存储器的半导体器件具有提高的可靠性。
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公开(公告)号：US20060186468A1
公开(公告)日：2006-08-24
申请号：US11350117
申请日：2006-02-09
申请人： Naohiro Hosoda , Tetsuo Adachi
发明人： Naohiro Hosoda , Tetsuo Adachi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546
摘要： Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.
摘要翻译： 提供一种半导体器件的制造方法，其具有以下步骤：以半导体衬底的形式层叠绝缘膜，用于形成浮栅电极的导体膜和另一绝缘膜，形成多个层叠图案 在所述多个层叠图案的侧表面上形成侧壁，通过干蚀刻去除任何两个相邻层叠图案之间的半导体衬底的损伤层，在两个相邻层叠图案之间的半导体衬底上形成绝缘膜，并形成多个 的辅助栅电极在两个相邻层叠图案之间的绝缘膜上自对准。 根据本发明，具有闪速存储器的半导体器件具有提高的可靠性。
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8.发明申请公开(公告)号：US20060001081A1
公开(公告)日：2006-01-05
申请号：US11166114
申请日：2005-06-27
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0491 , H01L27/11521
摘要： A leakage current flowing between data lines of a nonvolatile semiconductor memory is reduced. In a memory array of a nonvolatile semiconductor memory device having an AND type flash memory, a concave portion is formed in a junction isolation area between adjacent word limes and between adjacent assist gate wirings AGL, and the height of a main surface (first main surface) of a semiconductor substrate in the region where the concave portion is formed is made lower than that of the main surface (second main surface) of the semiconductor substrate to which an assist gate wiring is facing. As a result, it is possible to control the leakage current that flows between the drain line and source line in the aforementioned junction isolation region during operation of a flash memory.
摘要翻译： 在非易失性半导体存储器的数据线之间流动的漏电流减少。 在具有AND型闪速存储器的非易失性半导体存储器件的存储器阵列中，在相邻字灰度之间和相邻辅助栅极布线AGL之间的结隔离区域中形成凹部，并且在主表面（第一主表面 ）形成在形成有凹部的区域中的半导体衬底的低于辅助栅极布线所面对的半导体衬底的主表面（第二主表面）的厚度。 结果，可以在闪速存储器的操作期间控制在上述结隔离区域中的漏极线和源极线之间流动的漏电流。
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9.发明申请公开(公告)号：US20080226919A1
公开(公告)日：2008-09-18
申请号：US11720146
申请日：2005-11-07
申请人： Naohiro Hosoda , Shintaro Hikasa
发明人： Naohiro Hosoda , Shintaro Hikasa
IPC分类号： B32B27/00 , G11B23/107
CPC分类号： B65D85/672 , C08J5/18 , C08J2329/04 , Y10T428/1379 , Y10T428/31504
摘要： To provide a water-soluble film roll 3 having end faces 4 with masking materials 5 adhered thereto. By using the water-soluble film roll 3 and paying out a water-soluble film 1 while holding the masking materials 5 adhered to the end faces 4, it is possible to prevent moisture from adhering to the end faces 4 and to prevent the water-soluble film 1 from rupturing due to welding of the film 1 with itself. In this connection, the masking materials 5 are preferably a plastic film capable of being adhered to the end faces 4 with a pressure-sensitive adhesive.
摘要翻译： 提供具有附着有掩蔽材料5的端面4的水溶性薄膜卷3。 通过使用水溶性薄膜卷3并且在保持附着在端面4上的掩模材料5的同时支付水溶性薄膜1，可以防止水分附着在端面4上， 可溶性膜1由于膜1与其自身的焊接而破裂。 在这方面，掩模材料5优选是能够用压敏粘合剂粘附到端面4上的塑料膜。
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公开(公告)号：US09245900B2
公开(公告)日：2016-01-26
申请号：US13614853
申请日：2012-09-13
申请人： Naohiro Hosoda , Daisuke Okada , Kozo Katayama
发明人： Naohiro Hosoda , Daisuke Okada , Kozo Katayama
IPC分类号： H01L29/788 , H01L29/792 , H01L21/336 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42344 , H01L29/42364 , H01L29/66833 , H01L29/792
摘要： A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.
摘要翻译： 本发明的半导体器件具有形成在控制栅电极和半导体衬底之间的第一绝缘膜和形成在存储栅电极和半导体衬底之间以及控制栅电极和存储栅电极之间的第二绝缘膜， 其中具有电荷累积部分的第二绝缘膜。 第二绝缘膜具有第一膜，用作第一膜上的电荷蓄积部的第二膜和设置在第二膜上的第三膜。 第三膜具有位于控制栅电极和存储栅电极之间的侧壁膜和位于存储栅电极和半导体衬底之间的沉积膜。 在该结构中，能够增大第二绝缘膜的角部的距离，能够降低电场的浓度。
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