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    Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors
    3.
    发明授权
    Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors 有权
    绝缘体上半导体器件，具有埋入去耦电容器的器件和系统

    公开(公告)号：US08618633B2

    公开(公告)日：2013-12-31

    申请号：US13357322

    申请日：2012-01-24

    申请人： Badih El-Kareh

    发明人： Badih El-Kareh

    IPC分类号： H01L21/02

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

    摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

    Open source/drain junction field effect transistor
    4.
    发明授权
    Open source/drain junction field effect transistor 有权
    开路/漏极结场效应晶体管

    公开(公告)号：US07615425B2

    公开(公告)日：2009-11-10

    申请号：US11504412

    申请日：2006-08-15

    申请人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    发明人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    IPC分类号： H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/0607 ,  H01L29/66901

    摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

    摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

    Integrated BiCMOS semiconductor circuit
    5.
    发明授权
    Integrated BiCMOS semiconductor circuit 有权
    集成BiCMOS半导体电路

    公开(公告)号：US07498639B2

    公开(公告)日：2009-03-03

    申请号：US11233960

    申请日：2005-09-23

    申请人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl ,  Michael Schmitt

    发明人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl ,  Michael Schmitt

    IPC分类号： H01L31/112

    CPC分类号： H01L27/0623 ,  H01L21/76229 ,  H01L21/8249 ,  H01L27/0207

    摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.

    摘要翻译： 集成的BiCMOS半导体电路在硅中具有积极的护城河区域。 活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。 集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。 虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。

    Open source/drain junction field effect transistor
    6.
    发明申请
    Open source/drain junction field effect transistor 有权
    开路/漏极结场效应晶体管

    公开(公告)号：US20080042199A1

    公开(公告)日：2008-02-21

    申请号：US11504412

    申请日：2006-08-15

    申请人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    发明人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    IPC分类号： H01L27/12

    CPC分类号： H01L29/808 ,  H01L29/0607 ,  H01L29/66901

    摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

    摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

    Method of fabricating complementary bipolar transistors with SiGe base regions
    9.
    发明申请
    Method of fabricating complementary bipolar transistors with SiGe base regions 有权
    用SiGe基极区制造互补双极晶体管的方法

    公开(公告)号：US20050014341A1

    公开(公告)日：2005-01-20

    申请号：US10822078

    申请日：2004-04-08

    申请人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    发明人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    IPC分类号： H01L21/331 ,  H01L21/8228

    CPC分类号： H01L29/66242 ,  H01L21/82285

    摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.

    摘要翻译： 在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。 使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。