公开(公告)号：US20130240828A1

公开(公告)日：2013-09-19

申请号：US13729959

申请日：2012-12-28

申请人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA ,  Yusuke HIGASHI

发明人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA ,  Yusuke HIGASHI

IPC分类号： H01L29/32

CPC分类号： H01L29/32 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78696

摘要： A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.

摘要翻译： 根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的掩埋绝缘层，形成在掩埋绝缘层上并且包括狭窄部分和比窄部分大的两个宽部分的半导体层 并且分别连接到窄部分的一端和另一端，形成在窄部分的侧表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 直接在窄部下方的半导体衬底的杂质浓度高于窄部分的杂质浓度，并且直接在窄部下方的半导体衬底的杂质浓度高于直接在宽度以下的半导体衬底的杂质浓度 一部分。

公开(公告)号：US20120299100A1

公开(公告)日：2012-11-29

申请号：US13415592

申请日：2012-03-08

申请人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA

发明人： Kensuke OTA ,  Toshinori NUMATA ,  Masumi SAITOH ,  Chika TANAKA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/786 ,  H01L29/00 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

摘要翻译： 实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

公开(公告)号：US20120273747A1

公开(公告)日：2012-11-01

申请号：US13458042

申请日：2012-04-27

申请人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

发明人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

IPC分类号： H01L27/26 ,  H01L21/8239 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L27/101 ,  H01L27/1211 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.

摘要翻译： 根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。 第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。 被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。