公开(公告)号：US20130175490A1

公开(公告)日：2013-07-11

申请号：US13547645

申请日：2012-07-12

申请人： Haruka KUSAI ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

发明人： Haruka KUSAI ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

IPC分类号： H01L27/088 ,  H01L27/24 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/265 ,  H01L21/02

CPC分类号： H01L27/088 ,  G11C16/04 ,  G11C16/10 ,  H01L21/02367 ,  H01L21/265 ,  H01L21/32051 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/685 ,  H01L29/788 ,  H01L29/792 ,  H01L29/82

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。 结构和梁中的每一个包括沿垂直方向堆叠的半导体层。 梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

公开(公告)号：US09105838B2

公开(公告)日：2015-08-11

申请号：US13228753

申请日：2011-09-09

申请人： Takashi Haimoto ,  Reika Ichihara ,  Haruka Kusai

发明人： Takashi Haimoto ,  Reika Ichihara ,  Haruka Kusai

IPC分类号： G11C11/00 ,  H01L45/00 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

CPC分类号： H01L45/085 ,  G11C11/5614 ,  G11C13/0011 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148

摘要： According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode.

摘要翻译： 根据一个实施例，第一电极包括金属元件。 第二电极包括半导体元件。 第三电极包括金属元件。 第一可变电阻层布置在第一电极和第二电极之间，并且能够通过灯丝形成和第一电极的金属元件的溶解来可逆地改变电阻。 第二可变电阻层布置在第二电极和第三电极之间，并且能够通过灯丝形成和第三电极的金属元件的溶解来可逆地改变电阻。

公开(公告)号：US09087715B2

公开(公告)日：2015-07-21

申请号：US13547645

申请日：2012-07-12

申请人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

发明人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

IPC分类号： H01L27/115 ,  H01L27/088 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/24 ,  G11C16/04 ,  H01L29/66 ,  H01L29/68 ,  H01L29/788 ,  H01L29/792 ,  G11C16/10 ,  H01L29/82

CPC分类号： H01L27/088 ,  G11C16/04 ,  G11C16/10 ,  H01L21/02367 ,  H01L21/265 ,  H01L21/32051 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/685 ,  H01L29/788 ,  H01L29/792 ,  H01L29/82

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。 结构和梁中的每一个包括沿垂直方向堆叠的半导体层。 梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

公开(公告)号：US20130181184A1

公开(公告)日：2013-07-18

申请号：US13547567

申请日：2012-07-12

申请人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

发明人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

IPC分类号： H01L27/24 ,  H01L21/8234

CPC分类号： H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

公开(公告)号：US20130134372A1

公开(公告)日：2013-05-30

申请号：US13689026

申请日：2012-11-29

申请人： Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

发明人： Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

IPC分类号： H01L45/00 ,  H01L21/265

CPC分类号： H01L27/1157 ,  H01L21/265 ,  H01L21/845 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04

摘要： According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.

摘要翻译： 根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第 绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

公开(公告)号：US08432186B1

公开(公告)日：2013-04-30

申请号：US13484639

申请日：2012-05-31

申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

IPC分类号： H03K19/173

CPC分类号： H03K19/018585 ,  G11C5/146 ,  G11C16/10 ,  G11C16/12 ,  H03K19/1737

摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

摘要翻译： 一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于 擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入 低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

公开(公告)号：US20120091420A1

公开(公告)日：2012-04-19

申请号：US13052165

申请日：2011-03-21

申请人： Haruka KUSAI ,  Shosuke Fujii ,  Yasushi Nakasaki

发明人： Haruka KUSAI ,  Shosuke Fujii ,  Yasushi Nakasaki

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/33 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148

摘要： According to one embodiment a first variable resistance layer which is arranged between a second electrode and a first electrode and in which a first conductive filament is capable of growing based on metal supplied from the second electrode, and an n-th variable resistance layer which is arranged between an n-th electrode and an (n+1)-th electrode and in which an n-th conductive filament whose growth rate is different from the first conductive filament is capable of growing based on metal supplied from the (n+1)-th electrode are included, a configuration in which a plurality of conductive filaments is electrically connected in series between the first electrode layer and the (n+1)-th electrode layer is included, and a resistance is changed in a stepwise manner.

摘要翻译： 根据一个实施例，布置在第二电极和第一电极之间并且第一导电细丝能够基于从第二电极提供的金属生长的第一可变电阻层，以及第n可变电阻层，其是第 布置在第n电极和第（n + 1）电极之间，并且其中生长速度不同于第一导电细丝的第n导电细丝能够基于从第（n + 1）个 ）电极，包括在第一电极层和第（n + 1）电极层之间串联电连接多根导电丝的结构，并且电阻以逐步的方式改变。

公开(公告)号：US09076722B2

公开(公告)日：2015-07-07

申请号：US13547567

申请日：2012-07-12

申请人： Kiwamu Sakuma ,  Masahiro Kiyotoshi ,  Atsuhiro Kinoshita ,  Haruka Kusai

发明人： Kiwamu Sakuma ,  Masahiro Kiyotoshi ,  Atsuhiro Kinoshita ,  Haruka Kusai

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L27/24 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/22 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06

CPC分类号： H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括鳍式堆叠层结构。 每个结构包括沿垂直方向堆叠的半导体层。 辅助栅电极沿面内方向设置，并在结构垂直方向的一个表面上划分。

公开(公告)号：US08710580B2

公开(公告)日：2014-04-29

申请号：US13689026

申请日：2012-11-29

申请人： Kiwamu Sakuma ,  Haruka Kusai ,  Shosuke Fujii ,  Li Zhang ,  Masahiro Kiyotoshi ,  Masao Shingu

发明人： Kiwamu Sakuma ,  Haruka Kusai ,  Shosuke Fujii ,  Li Zhang ,  Masahiro Kiyotoshi ,  Masao Shingu

IPC分类号： H01L45/00 ,  H01L27/115 ,  H01L21/265

CPC分类号： H01L27/1157 ,  H01L21/265 ,  H01L21/845 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04

摘要： According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.

摘要翻译： 根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第 绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

公开(公告)号：US08710485B2

公开(公告)日：2014-04-29

申请号：US13458042

申请日：2012-04-27

申请人： Masumi Saitoh ,  Toshinori Numata ,  Kiwamu Sakuma ,  Haruka Kusai ,  Takayuki Ishikawa

发明人： Masumi Saitoh ,  Toshinori Numata ,  Kiwamu Sakuma ,  Haruka Kusai ,  Takayuki Ishikawa

IPC分类号： H01L29/06 ,  H01L47/00

CPC分类号： H01L21/823431 ,  H01L27/101 ,  H01L27/1211 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.

摘要翻译： 根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。 第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。 被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。