公开(公告)号：US5538922A

公开(公告)日：1996-07-23

申请号：US378990

申请日：1995-01-25

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60 ,  H01L21/46

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5219793A

公开(公告)日：1993-06-15

申请号：US709554

申请日：1991-06-03

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5061647A

公开(公告)日：1991-10-29

申请号：US597946

申请日：1990-10-12

申请人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

发明人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/7836

摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.

摘要翻译： 一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。 第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。 工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

公开(公告)号：US5210435A

公开(公告)日：1993-05-11

申请号：US745652

申请日：1991-08-16

申请人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

发明人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/7836

摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.

摘要翻译： 一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。 第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。 工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

公开(公告)号：US5246537A

公开(公告)日：1993-09-21

申请号：US876146

申请日：1992-04-30

申请人： Kent J. Cooper ,  Scott S. Roth ,  Wayne J. Ray ,  Howard C. Kirsch

发明人： Kent J. Cooper ,  Scott S. Roth ,  Wayne J. Ray ,  Howard C. Kirsch

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76227

摘要： A method requiring only a single mask results in an isolation oxide (50) which is the same size as, instead of becoming larger than, the dimension originally defined by the lithographic system. A buffer layer (14) is formed over the substrate (12). An oxidation resistant layer (16) is formed over the buffer layer (14). The oxidation resistant layer (16) is etched and a disposable sidewall spacer (30) is formed adjacent to the sidewall of the oxidation resistant layer (28), and a trench region is defined (36). The trench region (36) is etched to form a trench. The disposable sidewall spacer (30) is removed and a conformal layer (48) of oxidizable material is deposited over the trench sidewall (40) and the trench bottom surface (38). The conformal layer (48) is then oxidized to form electrical isolation in the isolation regions (26) of the substrate (12).

摘要翻译： 仅需要单个掩模的方法产生与原始由光刻系统定义的尺寸相同的尺寸的隔离氧化物（50），而不是变大。 在衬底（12）上形成缓冲层（14）。 在缓冲层（14）上形成抗氧化层（16）。 蚀刻抗氧化层（16），并且邻近抗氧化层（28）的侧壁形成一次侧壁间隔物（30），并且限定沟槽区域（36）。 蚀刻沟槽区域（36）以形成沟槽。 一次性侧壁间隔件（30）被去除，并且可氧化材料的共形层（48）沉积在沟槽侧壁（40）和沟槽底表面（38）上。 然后将保形层（48）氧化以在衬底（12）的隔离区域（26）中形成电隔离。

公开(公告)号：US5158910A

公开(公告)日：1992-10-27

申请号：US618204

申请日：1990-11-26

申请人： Kent J. Cooper ,  Michael P. Woo ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Michael P. Woo ,  Wayne J. Ray

IPC分类号： H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  Y10S148/106

摘要： Self-aligned and/or isolated contacts are formed in a semiconductor device, while simultaneously providing device planarization. In one form, an imagable material is deposited directly on a substrate material. The imagable material is patterned to form a sacrifical plug on a portion of the substrate material. A substantially planar insulating layer is then deposited overlying the substrate material. The plug formed of the imagable material is then removed, thereby exposing a portion of the substrate material and defining a contact opening. A conductive layer is deposited and patterned to complete formation of a contact.

摘要翻译： 在半导体器件中形成自对准和/或隔离的触点，同时提供器件平面化。 在一种形式中，可成像材料直接沉积在基底材料上。 可成像材料被图案化以在基底材料的一部分上形成牺牲塞。 然后将基本平坦的绝缘层沉积在衬底材料上。 然后移除由可成像材料形成的插头，从而露出基板材料的一部分并限定接触开口。 导电层被沉积并图案化以完成接触的形成。

公开(公告)号：USRE35294E

公开(公告)日：1996-07-09

申请号：US245131

申请日：1994-05-17

申请人： Barbara Vasquez ,  Michael P. Masquelier ,  Scott S. Roth ,  Wayne J. Ray

发明人： Barbara Vasquez ,  Michael P. Masquelier ,  Scott S. Roth ,  Wayne J. Ray

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/32 ,  Y10S148/117

摘要： A reduction in defects and lateral encroachment is obtained by .[.utilizing a high pressure oxidation in conjunction with.]. an oxidizable layer conformally deposited over an oxidation mask. .[.The.]. .Iadd.In one embodiment, the .Iaddend.use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited..Iadd.Alternately, lateral encroachment can be controlled by intentionally growing an oxide layer on the substrate surface. .Iaddend.

摘要翻译： 缺陷和横向侵蚀的减少通过[利用高压氧化与]氧化掩膜上共形沉积的可氧化层来获得。 在一个实施方案中，使用高压氧化提供形成LOCOS氧化物而不形成缺陷。 存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。 在本实施例中，可以除去可充当氧扩散管的任何氧化物。 因此，表现为名义上或没有横向侵占。 或者，可以通过在衬底表面上有意地生长氧化物层来控制横向侵蚀。

公开(公告)号：US5272117A

公开(公告)日：1993-12-21

申请号：US986303

申请日：1992-12-07

申请人： Scott S. Roth ,  Wayne J. Ray ,  Howard C. Kirsch

发明人： Scott S. Roth ,  Wayne J. Ray ,  Howard C. Kirsch

IPC分类号： H01L21/768 ,  H01L21/465

CPC分类号： H01L21/76819

摘要： A method for forming a planarized layer of material starts by providing a substrate (12). An integrated circuit layer (14) is formed overlying the substrate (12). A first layer of material (16) is formed overlying the integrated circuit layer (14). An etch stop layer (18) is formed overlying the layer of material (16) and etched to form sidewall formations or spacers. A second layer of material (20) is formed overlying the layer of material (16) and the etch stop layer (18). Planarization, polishing, or etch-back processing is performed using the etch stop layer (18) to endpoint. The resulting planarized layer has a thickness which is determined accurately by the etch stop layer (18).

摘要翻译： 用于形成平坦化材料层的方法通过提供衬底（12）开始。 在衬底（12）上形成集成电路层（14）。 第一层材料（16）形成在该集成电路层（14）上。 形成覆盖在材料层（16）上的蚀刻停止层（18），并被蚀刻以形成侧壁结构或间隔物。 形成第二层材料（20），覆盖材料层（16）和蚀刻停止层（18）。 使用蚀刻停止层（18）至端点进行平面化，抛光或回蚀刻处理。 得到的平坦化层具有由蚀刻停止层（18）精确确定的厚度。

公开(公告)号：US4997790A

公开(公告)日：1991-03-05

申请号：US566185

申请日：1990-08-13

申请人： Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

发明人： Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L24/11 ,  Y10S148/105 ,  Y10S148/161

摘要： A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members. A conductive layer is deposited onto the device and patterned, thereby forming a self-aligned contact.

摘要翻译： 在多层半导体器件中形成自对准接触。 在一种形式中，形成覆盖衬底材料的导电构件，并且沉积覆盖衬底材料和导电构件的第一绝缘层。 将材料膜沉积在第一绝缘层上，并且将材料膜图案化以在要进行接触的区域中形成牺牲插塞。 第二绝缘层沉积在器件上，并且器件基本上是平面的。 将第二绝缘层回蚀刻以暴露牺牲插头。 通过选择性地蚀刻该器件以使得第一绝缘层和第二绝缘层基本上保持不变而去除牺牲插塞。 执行器件的各向异性蚀刻以暴露要在其上形成触点的衬底材料的区域，并且同时沿着导电构件的边缘形成侧壁间隔物。 导电层沉积在器件上并图案化，从而形成自对准接触。