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77 条记录 (耗时 0.049 秒)

    Damping of LC ringing in IC (integrated circuit) power distribution systems
    2.
    发明授权
    Damping of LC ringing in IC (integrated circuit) power distribution systems 失效
    IC（集成电路）配电系统中LC振荡的阻尼

    公开(公告)号：US06963240B2

    公开(公告)日：2005-11-08

    申请号：US10707171

    申请日：2003-11-25

    申请人： Anthony R. Bonaccio ,  Allen P. Haar ,  Michael A. Sorna ,  Ivan L. Wemple ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Allen P. Haar ,  Michael A. Sorna ,  Ivan L. Wemple ,  Stephen D. Wyatt

    IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

    CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

    摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

    摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

    Method and apparatus for storing circuit calibration information
    3.
    发明授权
    Method and apparatus for storing circuit calibration information 失效
    存储电路校准信息的方法和装置

    公开(公告)号：US07454305B2

    公开(公告)日：2008-11-18

    申请号：US11164040

    申请日：2005-11-08

    申请人： Anthony R. Bonaccio ,  Allen P. Haar ,  Joseph A. Iadanza ,  Douglas W. Stout ,  Ivan L. Wemple

    发明人： Anthony R. Bonaccio ,  Allen P. Haar ,  Joseph A. Iadanza ,  Douglas W. Stout ,  Ivan L. Wemple

    IPC分类号： G01R31/00 ,  G06F19/00

    CPC分类号： G01R31/2884 ,  G01R35/005

    摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

    摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在各个芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

    Pseudo-random binary sequence checker with automatic synchronization
    4.
    发明授权
    Pseudo-random binary sequence checker with automatic synchronization 有权
    具有自动同步的伪随机二进制序列检查器

    公开(公告)号：US07219113B2

    公开(公告)日：2007-05-15

    申请号：US10605381

    申请日：2003-09-26

    申请人： Anthony R. Bonaccio ,  Allen P. Haar

    发明人： Anthony R. Bonaccio ,  Allen P. Haar

    IPC分类号： G06F7/58

    CPC分类号： G01R31/318385 ,  G01R31/31703 ,  G01R31/31728 ,  G06F7/584 ,  G06F2207/582

    摘要： A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.

    摘要翻译： 公开了具有自动同步的伪随机二进制序列检验器。 伪随机二进制序列检查器包括接收器，同步器和比较器。 接收机能够以并行方式一次接收由伪随机二进制序列生成器生成的伪随机二进制序列，每个n位。 同步器自动将接收器的状态与伪随机二进制序列内的n位采样同步，并计算伪随机二进制序列内的所有随后的n位采样。 比较器将伪随机二进制序列中随后计算的n位采样与伪随机二进制序列中的下一个接下来的接收到的n位采样进行比较，以指示如果每个计算的n位采样在 伪随机二进制序列不等于伪随机二进制序列内的相应接收的n位样本。

    Redundant input/output driver circuit
    7.
    发明授权
    Redundant input/output driver circuit 失效
    冗余输入/输出驱动电路

    公开(公告)号：US06177809B1

    公开(公告)日：2001-01-23

    申请号：US09322470

    申请日：1999-05-28

    申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    IPC分类号： H03K19094

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

    摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。