利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

167 条记录 (耗时 0.041 秒)

    Redundant input/output driver circuit
    3.
    发明授权
    Redundant input/output driver circuit 失效
    冗余输入/输出驱动电路

    公开(公告)号：US06177809B1

    公开(公告)日：2001-01-23

    申请号：US09322470

    申请日：1999-05-28

    申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    IPC分类号： H03K19094

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

    摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。

    Integrated circuit amplifier device and method using FET tunneling gate current
    6.
    发明授权
    Integrated circuit amplifier device and method using FET tunneling gate current 失效
    集成电路放大器器件及使用FET隧道栅极电流的方法

    公开(公告)号：US07167053B2

    公开(公告)日：2007-01-23

    申请号：US10904238

    申请日：2004-10-29

    申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Kiran V. Chatty ,  John A. Fifield

    发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Kiran V. Chatty ,  John A. Fifield

    IPC分类号： H03F3/16 ,  H03F3/45 ,  H03G3/12

    CPC分类号： H03F3/16 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45468

    摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.

    摘要翻译： 在示例性实施例中，集成电路放大器包括被配置为具有源极退化的公共源极放大器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器 。 隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极退化的公共源极放大器，以便设置放大器的输出电导。

    DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF
    8.
    发明申请
    DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF 有权
    用于变换输入电压以获得输入和输出功能与系统之间的线性的设计结构及其方法

    公开(公告)号：US20090243733A1

    公开(公告)日：2009-10-01

    申请号：US12057686

    申请日：2008-03-28

    申请人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

    发明人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

    IPC分类号： H03L7/00

    CPC分类号： H03L7/099

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.

    摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。 还公开了一种实现这种结构的系统和方法。

    Error correcting logic system
    10.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07642813B2

    公开(公告)日：2010-01-05

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。