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34 条记录 (耗时 0.035 秒)

    Damping of LC ringing in IC (integrated circuit) power distribution systems
    2.
    发明授权
    Damping of LC ringing in IC (integrated circuit) power distribution systems 失效
    IC（集成电路）配电系统中LC振荡的阻尼

    公开(公告)号：US06963240B2

    公开(公告)日：2005-11-08

    申请号：US10707171

    申请日：2003-11-25

    申请人： Anthony R. Bonaccio ,  Allen P. Haar ,  Michael A. Sorna ,  Ivan L. Wemple ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Allen P. Haar ,  Michael A. Sorna ,  Ivan L. Wemple ,  Stephen D. Wyatt

    IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

    CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

    摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

    摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

    On chip resistor calibration structure and method
    3.
    发明授权
    On chip resistor calibration structure and method 失效
    片上电阻校准结构及方法

    公开(公告)号：US06825490B1

    公开(公告)日：2004-11-30

    申请号：US10605567

    申请日：2003-10-09

    申请人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

    发明人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

    IPC分类号： H01L2358

    CPC分类号： G01R35/005

    摘要： A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.

    摘要翻译： 确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。 半导体器件包括电容器，校准电阻器和校准电路。 施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。 校准电路适于测量对电容器充电所需的实际时间。 校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。

    Structure and method for providing gate leakage isolation locally within analog circuits
    9.
    发明授权
    Structure and method for providing gate leakage isolation locally within analog circuits 失效
    在模拟电路中局部提供栅极泄漏隔离的结构和方法

    公开(公告)号：US07268632B2

    公开(公告)日：2007-09-11

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    IPC分类号： H03L7/00 ,  H03L7/099 ,  H03B5/18

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

    DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF
    10.
    发明申请
    DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF 有权
    用于变换输入电压以获得输入和输出功能与系统之间的线性的设计结构及其方法

    公开(公告)号：US20090243733A1

    公开(公告)日：2009-10-01

    申请号：US12057686

    申请日：2008-03-28

    申请人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

    发明人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

    IPC分类号： H03L7/00

    CPC分类号： H03L7/099

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.

    摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。 还公开了一种实现这种结构的系统和方法。