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公开(公告)号：US08013342B2
公开(公告)日：2011-09-06
申请号：US11939612
申请日：2007-11-14
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/04
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US07670927B2
公开(公告)日：2010-03-02
申请号：US11383586
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L21/30
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US20070267723A1
公开(公告)日：2007-11-22
申请号：US11383586
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US20090121260A1
公开(公告)日：2009-05-14
申请号：US11939612
申请日：2007-11-14
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/78
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US20110302542A1
公开(公告)日：2011-12-08
申请号：US13192608
申请日：2011-07-28
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US20110241082A1
公开(公告)日：2011-10-06
申请号：US13164173
申请日：2011-06-20
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L27/085 , H01L23/532
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US08471306B2
公开(公告)日：2013-06-25
申请号：US13192608
申请日：2011-07-28
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/80 , H01L29/04 , H01L31/036
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US08421126B2
公开(公告)日：2013-04-16
申请号：US13164173
申请日：2011-06-20
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L27/085
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 半导体结构。 半导体结构包括两个绝缘体上硅晶片，其中制造了器件，并且利用掩埋氧化物层将它们背靠背接合，或者使用衬底间介质层和掩埋氧化物层之间的结合层将它们背靠背连接。 这些结构包括形成在上晶片中的触点与下晶片中的器件和形成在上晶片上的布线电平。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US07989312B2
公开(公告)日：2011-08-02
申请号：US12612957
申请日：2009-11-05
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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公开(公告)号：US20100044759A1
公开(公告)日：2010-02-25
申请号：US12612957
申请日：2009-11-05
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/786 , H01L21/18 , H01L21/768 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
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