-
公开(公告)号:US08471306B2
公开(公告)日:2013-06-25
申请号:US13192608
申请日:2011-07-28
申请人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号: H01L29/80 , H01L29/04 , H01L31/036
CPC分类号: G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译: 双面集成电路芯片,制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅,并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触,并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
-
公开(公告)号:US08013342B2
公开(公告)日:2011-09-06
申请号:US11939612
申请日:2007-11-14
申请人: Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人: Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号: H01L29/04
CPC分类号: G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译: 双面集成电路芯片,制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅,并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触,并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
-
公开(公告)号:US08004289B2
公开(公告)日:2011-08-23
申请号:US12198221
申请日:2008-08-26
申请人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号: G01R27/26 , G01R31/308
CPC分类号: H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译: 用于对准晶片的结构及其操作方法。 该结构包括(a)包括第一电容耦合结构的第一半导体晶片和(b)包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离,同时第一和第二半导体晶片经由公共表面彼此直接物理接触,则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。
-
公开(公告)号:US20080308948A1
公开(公告)日:2008-12-18
申请号:US12198221
申请日:2008-08-26
申请人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
CPC分类号: H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译: 用于对准晶片的结构及其操作方法。 该结构包括(a)包括第一电容耦合结构的第一半导体晶片和(b)包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离,同时第一和第二半导体晶片经由公共表面彼此直接物理接触,则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。
-
公开(公告)号:US07193423B1
公开(公告)日:2007-03-20
申请号:US11275112
申请日:2005-12-12
申请人: Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人: Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
CPC分类号: H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译: 用于对准晶片的结构及其操作方法。 该结构包括(a)包括第一电容耦合结构的第一半导体晶片和(b)包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离,同时第一和第二半导体晶片经由公共表面彼此直接物理接触,则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。
-
公开(公告)号:US08421126B2
公开(公告)日:2013-04-16
申请号:US13164173
申请日:2011-06-20
申请人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号: H01L27/085
CPC分类号: H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译: 半导体结构。 半导体结构包括两个绝缘体上硅晶片,其中制造了器件,并且利用掩埋氧化物层将它们背靠背接合,或者使用衬底间介质层和掩埋氧化物层之间的结合层将它们背靠背连接。 这些结构包括形成在上晶片中的触点与下晶片中的器件和形成在上晶片上的布线电平。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
-
公开(公告)号:US08026606B2
公开(公告)日:2011-09-27
申请号:US12547002
申请日:2009-08-25
IPC分类号: H01L21/00
CPC分类号: H01L23/53238 , H01L21/76801 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.
摘要翻译: 一种结构及其形成方法。 该结构包括(a)层间电介质层(ILD)层; (b)位于ILD层中的第一导电线和第二导电线; (c)位于ILD层中的扩散阻挡区域。 扩散阻挡区(i)物理隔离,(ii)电耦合在一起,和(iii)与第一和第二导电线直接物理接触。 第一和第二导电线各自包括第一导电材料。 扩散阻挡区域包括不同于第一导电材料的第二导电材料。 扩散阻挡区域适于防止第一导电材料通过扩散阻挡区域的扩散。
-
公开(公告)号:US07989312B2
公开(公告)日:2011-08-02
申请号:US12612957
申请日:2009-11-05
申请人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人: Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
CPC分类号: H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译: 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅,并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触,并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
-
公开(公告)号:US20090121260A1
公开(公告)日:2009-05-14
申请号:US11939612
申请日:2007-11-14
申请人: Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人: Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号: H01L29/78
CPC分类号: G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译: 双面集成电路芯片,制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅,并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触,并在上晶片上形成布线层。 下晶片可以包括布线水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。
-
公开(公告)号:US07474104B2
公开(公告)日:2009-01-06
申请号:US11557668
申请日:2006-11-08
申请人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffee , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人: Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffee , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号: G01R27/26 , H01L23/544
CPC分类号: H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译: 用于对准晶片的结构及其操作方法。 该结构包括(a)包括第一电容耦合结构的第一半导体晶片和(b)包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离,同时第一和第二半导体晶片经由公共表面彼此直接物理接触,则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。
-
-
-
-
-
-
-
-
-