公开(公告)号：US20060036826A1

公开(公告)日：2006-02-16

申请号：US10903182

申请日：2004-07-30

申请人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

摘要翻译： 用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的操作是内存模块数据速率的四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

公开(公告)号：US20060036827A1

公开(公告)日：2006-02-16

申请号：US10903188

申请日：2004-07-30

申请人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F11/201 ,  G06F11/104

摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

公开(公告)号：US20070255902A1

公开(公告)日：2007-11-01

申请号：US11773660

申请日：2007-07-05

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F13/4022

摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

公开(公告)号：US20060026349A1

公开(公告)日：2006-02-02

申请号：US10903178

申请日：2004-07-30

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F13/4022

摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

公开(公告)号：US20060095701A1

公开(公告)日：2006-05-04

申请号：US10977038

申请日：2004-10-29

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1689

摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

公开(公告)号：US20060095671A1

公开(公告)日：2006-05-04

申请号：US10977846

申请日：2004-10-29

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F13/00

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

公开(公告)号：US20080046796A1

公开(公告)日：2008-02-21

申请号：US11851527

申请日：2007-09-07

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： H03M13/00

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。

公开(公告)号：US20080016280A1

公开(公告)日：2008-01-17

申请号：US11772922

申请日：2007-07-03

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F12/08

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

公开(公告)号：US20080016281A1

公开(公告)日：2008-01-17

申请号：US11780048

申请日：2007-07-19

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F13/00

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

公开(公告)号：US20070300129A1

公开(公告)日：2007-12-27

申请号：US11851485

申请日：2007-09-07

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： G11C29/52

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。