公开(公告)号：US20120116737A1

公开(公告)日：2012-05-10

申请号：US13329852

申请日：2011-12-19

申请人： Kevin J. Bowers ,  Ron O. Dror ,  David E. Shaw ,  Martin M. Deneroff ,  Richard H. Larson ,  John K. Salmon

发明人： Kevin J. Bowers ,  Ron O. Dror ,  David E. Shaw ,  Martin M. Deneroff ,  Richard H. Larson ,  John K. Salmon

IPC分类号： G06F17/10

CPC分类号： G06F9/30 ,  G06F15/76 ,  G16B15/00 ,  G16C10/00

摘要： A generalized approach to particle interaction can confer advantages over previously described method in terms of one or more of communications bandwidth and latency and memory access characteristics. These generalizations can involve one or more of at least spatial decomposition, import region rounding, and multiple zone communication scheduling. An architecture for computation of particle interactions makes use various forms of parallelism. In one implementation, the parallelism involves using multiple computation nodes arranged according to a geometric partitioning of a simulation volume.

摘要翻译： 在通信带宽和延迟和存储器访问特性中的一个或多个方面，通用的粒子交互方法可以赋予先前描述的方法的优点。 这些概括可以涉及至少空间分解，导入区域舍入和多区域通信调度中的一个或多个。 用于计算粒子相互作用的架构使用各种形式的并行性。 在一个实现中，并行性涉及使用根据模拟体积的几何划分排列的多个计算节点。

公开(公告)号：US20130091341A1

公开(公告)日：2013-04-11

申请号：US13680962

申请日：2012-11-19

申请人： David E. Shaw ,  Martin M. Deneroff ,  Ron O. Dror ,  Richard H. Larson ,  John K. Salmon

发明人： David E. Shaw ,  Martin M. Deneroff ,  Ron O. Dror ,  Richard H. Larson ,  John K. Salmon

IPC分类号： G06F15/76

CPC分类号： G06F9/30 ,  G06F15/76 ,  G06F19/16 ,  G06F19/701

摘要： A computation system for computing interactions in a multiple-body simulation includes an array of processing modules arranged into one or more serially interconnected processing groups of the processing modules. Each of the processing modules includes storage for data elements and includes circuitry for performing pairwise computations between data elements each associated with a spatial location. Each of the pairwise computations makes use of a data element from the storage of the processing module and a data element passing through the serially interconnected processing modules. Each of the processing modules includes circuitry for selecting the pairs of data elements according to separations between spatial locations associated with the data elements.

摘要翻译： 用于计算多体仿真中的交互的计算系统包括布置在处理模块的一个或多个串联互连处理组中的处理模块阵列。 每个处理模块包括用于数据元素的存储器，并且包括用于在每个与空间位置相关联的数据元素之间执行成对计算的电路。 每个成对计算利用来自处理模块的存储的数据元素和通过串行互连的处理模块的数据元素。 每个处理模块包括用于根据与数据元素相关联的空间位置之间的分离来选择数据元素对的电路。

公开(公告)号：US09747099B2

公开(公告)日：2017-08-29

申请号：US13680962

申请日：2012-11-19

申请人： David E. Shaw ,  Martin M. Deneroff ,  Ron O. Dror ,  Richard H. Larson ,  John K. Salmon

发明人： David E. Shaw ,  Martin M. Deneroff ,  Ron O. Dror ,  Richard H. Larson ,  John K. Salmon

IPC分类号： G06F17/10 ,  G06F9/30 ,  G06F19/00 ,  G06F15/76 ,  G06F19/16

CPC分类号： G06F9/30 ,  G06F15/76 ,  G06F19/16 ,  G06F19/701

摘要： A computation system for computing interactions in a multiple-body simulation includes an array of processing modules arranged into one or more serially interconnected processing groups of the processing modules. Each of the processing modules includes storage for data elements and includes circuitry for performing pairwise computations between data elements each associated with a spatial location. Each of the pairwise computations makes use of a data element from the storage of the processing module and a data element passing through the serially interconnected processing modules. Each of the processing modules includes circuitry for selecting the pairs of data elements according to separations between spatial locations associated with the data elements.

公开(公告)号：US07181589B2

公开(公告)日：2007-02-20

申请号：US10835855

申请日：2004-04-30

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  John Carter ,  Lixin Zhang ,  Michael Parker

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  John Carter ,  Lixin Zhang ,  Michael Parker

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/1027

摘要： An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

摘要翻译： 地址转换单元使用翻译后备缓冲器或分段缓冲器从虚拟地址生成用于访问存储器的物理地址。 如果虚拟地址落在预定范围内，则地址转换单元将使用分段缓冲器来生成物理地址。 在生成物理地址时，存储器将根据由处理器处理的指令从数据接收数据或向处理器提供数据。

公开(公告)号：US06578115B2

公开(公告)日：2003-06-10

申请号：US10047347

申请日：2002-01-14

申请人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

发明人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

IPC分类号： G06F1208

CPC分类号： G06F11/2051 ,  G06F12/0808 ,  G06F12/0817

摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.

公开(公告)号：US06339812B1

公开(公告)日：2002-01-15

申请号：US09410139

申请日：1999-09-30

申请人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

发明人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

IPC分类号： G06F1208

CPC分类号： G06F11/2051 ,  G06F12/0808 ,  G06F12/0817

摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.

摘要翻译： 计算机系统（10）中的节点控制器（12）包括处理器接口单元（24），存储器目录接口单元（22）和局部块单元（28）。 响应于与存储器目录接口单元（22）相关联的存储器（17）中的存储器位置被改变，处理器接口单元（24）生成用于传送到存储器目录接口单元（22）的无效请求。 存储器目录接口单元（22）将无效请求和无效请求影响的处理器（16）的标识提供给本地块单元（28）。 本地块单元（28）确定在计算机系统（10）中存在哪个已识别的处理器（16），并为每个当前处理器（16）生成用于传送的无效消息。 本处理器（16）中的每一个处理它们的无效消息，并产生用于传送到产生无效请求的处理器接口单元（24）的确认消息。 本地块单元（28）确定在计算机系统（10）中哪个识别的处理器（16）不存在，并为每个不存在的处理器（16）生成确认消息。 每个确认消息被传送到产生无效请求的处理器接口单元（24）。

公开(公告)号：US20130080709A1

公开(公告)日：2013-03-28

申请号：US13683367

申请日：2012-11-21

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器都不可见。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US08321634B2

公开(公告)日：2012-11-27

申请号：US13084280

申请日：2011-04-11

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US20090113172A1

公开(公告)日：2009-04-30

申请号：US12121941

申请日：2008-05-16

申请人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

发明人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

IPC分类号： G06F9/02

CPC分类号： G06F15/17312 ,  G06F15/17343 ,  G06F15/17381 ,  H04L45/14 ,  H04L67/1002

摘要： A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

摘要翻译： 提供了一种用于在可扩展多处理器系统内互连多个处理元件节点的系统和方法。 每个处理元件节点包括至少一个处理器和存储器。 可扩展互连网络包括互连集群中的处理元件节点的物理通信链路。 可伸缩互连网络中的第一组路由器在多个处理单元节点之间路由消息。 可扩展互连网络中的一个或多个元变换器在第一组路由器之间路由消息，使得第一集群中的每个路由器通过一个或多个元变换器连接到所有其他集群。

公开(公告)号：US06829666B1

公开(公告)日：2004-12-07

申请号：US09408874

申请日：1999-09-29

申请人： Martin M. Deneroff ,  Steve Dean ,  Timothy S. McCann ,  John Brennan ,  Dave Parry ,  John Mashey

发明人： Martin M. Deneroff ,  Steve Dean ,  Timothy S. McCann ,  John Brennan ,  Dave Parry ,  John Mashey

IPC分类号： G06F1338

CPC分类号： G06F15/17343 ,  G06F15/17381

摘要： A distributed, shared memory computer architecture that is organized into a set of functionally independent processing nodes operating in a global, shared address space. Each node has one or more local processors, local memory and includes a common communication interface for communicating with other modules within the system via a message protocol. The common communication interface provides a single high-speed communications center within each node to operatively couple the node to one or more external processing nodes, an external routing module, an input/output (I/O) module. The common communication interface that facilitates the ability to incrementally add and swap the nodes of the system without disrupting the overall computing resources of the system.

摘要翻译： 分布式共享存储器计算机体系结构，被组织成一组在全局共享地址空间中运行的功能独立的处理节点。 每个节点具有一个或多个本地处理器，本地存储器，并且包括用于经由消息协议与系统内的其他模块通信的公共通信接口。 公共通信接口在每个节点内提供单个高速通信中心，以将节点可操作地耦合到一个或多个外部处理节点，外部路由模块，输入/输出（I / O）模块。 通用通信接口，有助于增加和交换系统节点的能力，而不会中断系统的整体计算资源。