公开(公告)号：US07071103B2

公开(公告)日：2006-07-04

申请号：US10710737

申请日：2004-07-30

申请人： Kevin K. Chan ,  Huajie Chen ,  Michael A. Gribelyuk ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Ryan M. Mitchell ,  Renee T. Mo ,  Dan M. Mocuta ,  Werner A. Rausch ,  Paul A. Ronsheim ,  Henry K. Utomo

发明人： Kevin K. Chan ,  Huajie Chen ,  Michael A. Gribelyuk ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Ryan M. Mitchell ,  Renee T. Mo ,  Dan M. Mocuta ,  Werner A. Rausch ,  Paul A. Ronsheim ,  Henry K. Utomo

IPC分类号： H01L21/44

CPC分类号： H01L21/28044 ,  H01L21/324

摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

摘要翻译： 本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。 在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。 使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

公开(公告)号：US07247546B2

公开(公告)日：2007-07-24

申请号：US10710826

申请日：2004-08-05

申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith Fogel ,  Ryan M. Mitchell ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith Fogel ,  Ryan M. Mitchell ,  Devendra K. Sadana

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L31/117

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

摘要翻译： 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。 组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。 该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。 对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

公开(公告)号：US07718231B2

公开(公告)日：2010-05-18

申请号：US10674647

申请日：2003-09-30

申请人： Kwang Su Choe ,  Keith E. Fogel ,  Siegfried L. Maurer ,  Ryan M. Mitchell ,  Devendra K. Sadana

发明人： Kwang Su Choe ,  Keith E. Fogel ,  Siegfried L. Maurer ,  Ryan M. Mitchell ,  Devendra K. Sadana

IPC分类号： C23C14/10 ,  C23C14/48 ,  C23C14/58 ,  H01L21/762

CPC分类号： H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

摘要： A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

摘要翻译： 提供了一种制造在含Si的上层下方具有薄而均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。