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1.发明授权Method of forming strained silicon materials with improved thermal conductivity 有权形成具有改善导热性的应变硅材料的方法公开(公告)号：US07247546B2
公开(公告)日：2007-07-24
申请号：US10710826
申请日：2004-08-05
IPC分类号： H01L21/20 , H01L21/36 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译： 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。 组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。 该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。 对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。
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公开(公告)号：US08053759B2
公开(公告)日：2011-11-08
申请号：US12539248
申请日：2009-08-11
IPC分类号： H01L29/30
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A substrate material including a Si-containing substrate and an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate. The substrate material further includes a substantially relaxed SiGe alloy layer present atop the insulating region, wherein the substantially relaxed SiGe alloy layer has a planar defect density from about 5000 defects/cm−2 or less. The substrate material may be employed in a heterostructure, in which a strained Si layer is present atop the substantially relaxed SiGe alloy layer of the substrate material.
摘要翻译： 包含含Si衬底和耐Ge扩散的绝缘区的衬底材料存在于含Si衬底顶部。 衬底材料还包括存在于绝缘区域顶部的基本弛豫的SiGe合金层，其中基本上松弛的SiGe合金层具有约5000个缺陷/ cm -2或更小的平面缺陷密度。 衬底材料可以用于异质结构，其中应变Si层存在于衬底材料的基本上松弛的SiGe合金层顶上。
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3.发明授权Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer 失效包括基本上松弛的低缺陷密度SiGe层的半导体异质结构公开(公告)号：US07507988B2
公开(公告)日：2009-03-24
申请号：US11619040
申请日：2007-01-02
IPC分类号： H01L29/06
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.
摘要翻译： 提供了异质结构，其包括位于衬底上的绝缘区域上的基本上松弛的SiGe层。 基本上松弛的SiGe层具有约2000nm或更小的厚度，约50至约80％的测量晶格弛豫和小于约108缺陷/ cm 2的缺陷密度。 应变外延Si层位于基本上松弛的SiGe层之上，并且至少一个交替堆叠包括位于应变外延Si层上的底部松弛SiGe层和顶部应变Si层。
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公开(公告)号：US07348253B2
公开(公告)日：2008-03-25
申请号：US10855915
申请日：2004-05-27
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。
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5.发明授权Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density 失效形成具有高松弛和低堆垛层错缺陷密度的薄SGOI晶片的方法公开(公告)号：US07550370B2
公开(公告)日：2009-06-23
申请号：US10597066
申请日：2004-01-16
IPC分类号： H01L21/00
CPC分类号： H01L21/76256 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/31658 , H01L21/84 , H01L29/1054 , H01L29/78687
摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.
摘要翻译： 一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。 进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。 然后将SiGe层变薄至所需的最终厚度。 稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。 因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。 然后在薄SGOI晶片上沉积一层Si。 稀释方法包括低温（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。 由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片 和GeH4。
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公开(公告)号：US20100032684A1
公开(公告)日：2010-02-11
申请号：US12539248
申请日：2009-08-11
IPC分类号： H01L29/267 , H01L29/161 , H01L29/165
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
摘要翻译： 公开了一种制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si衬底的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。 还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。
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7.发明授权SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth 有权SiGe晶格工程使用氧化，稀化和外延再生长的组合公开(公告)号：US07026249B2
公开(公告)日：2006-04-11
申请号：US10448954
申请日：2003-05-30
IPC分类号： H01L21/302
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/02532 , H01L21/02664 , Y10T428/12674
摘要： The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.
摘要翻译： 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。
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公开(公告)号：US07679141B2
公开(公告)日：2010-03-16
申请号：US12027561
申请日：2008-02-07
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。
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公开(公告)号：US06989058B2
公开(公告)日：2006-01-24
申请号：US10654232
申请日：2003-09-03
IPC分类号： C30B25/02
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。
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公开(公告)号：US07816664B2
公开(公告)日：2010-10-19
申请号：US12139080
申请日：2008-06-13
IPC分类号： H01L29/06
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.
摘要翻译： 描述了可用作应变Si的模板的高质量，基本上松弛的绝缘体上硅衬底材料。 基本上松弛的绝缘体上硅衬底包括含硅衬底，在含Si衬底顶部存在耐Ge扩散的绝缘区域和存在于绝缘区域顶部的基本弛豫的SiGe层。 绝缘区域包括由热氧化物组成的上部区域，并且基本上松弛的SiGe层具有约2000nm或更小的厚度。
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