公开(公告)号：US08298843B2

公开(公告)日：2012-10-30

申请号：US12943345

申请日：2010-11-10

申请人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-Soo Jung

发明人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-Soo Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/40 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode.

摘要翻译： 阵列基板在基板上包括由金属材料形成的第一和第二线; 连接到第一线的栅电极; 在第一和第二线路上的栅极绝缘层和栅电极，并且包括暴露衬底并定位在第一和第二线之间的沟槽; 栅极绝缘层上的半导体层，并对应于栅电极; 跨越第一和第二线路以及栅极绝缘层的数据线; 连接到数据线的源电极; 与源电极间隔开的漏电极; 数据线上的钝化层，源电极和漏电极，并且包括开口，所述开口暴露栅极绝缘层和漏电极; 以及位于栅极绝缘层上且位于开口中且与漏电极接触的像素电极。

公开(公告)号：US20070194381A1

公开(公告)日：2007-08-23

申请号：US11708321

申请日：2007-02-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： H01L23/62

CPC分类号： H01L23/34 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  H01L2924/0002 ,  H01L2924/00

摘要： An example embodiment of the memory integrated circuit device may include a first temperature sensing unit, a first voltage adjusting unit, and a MOS back bias voltage outputting unit. The first voltage adjusting unit may be configured to output a voltage based on an output signal of the temperature sensing unit such that the voltage output changes based on changes in a sensed temperature. The MOS back bias voltage outputting unit may be configured to receive the voltage output by the voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit.

摘要翻译： 存储器集成电路器件的示例性实施例可以包括第一温度感测单元，第一电压调节单元和MOS背偏置电压输出单元。 第一电压调整单元可以被配置为基于温度感测单元的输出信号输出电压，使得电压输出基于感测温度的变化而改变。 MOS背偏置电压输出单元可以被配置为接收由电压调节单元输出的电压，并且被配置为基于第一电压调节单元输出的电压来输出MOS反向偏置电压。

公开(公告)号：US20060192607A1

公开(公告)日：2006-08-31

申请号：US11360106

申请日：2006-02-22

申请人： Ki-Chul Chun ,  Chang-Ho Shin

发明人： Ki-Chul Chun ,  Chang-Ho Shin

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/075

摘要： A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

公开(公告)号：US07091758B2

公开(公告)日：2006-08-15

申请号：US10834851

申请日：2004-04-30

申请人： Ki-Chul Chun ,  Jae-Yoon Sim

发明人： Ki-Chul Chun ,  Jae-Yoon Sim

IPC分类号： H03K17/22

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

摘要翻译： 半导体集成电路可以包括内部电路和用于产生上电复位信号的上电复位电路，以在通电时初始化内部电路。 在上电时，上电复位电路延迟上电复位信号从第一电平转换到第二电平，直到电源电压达到检测电压之后的给定持续时间。

公开(公告)号：US07079425B2

公开(公告)日：2006-07-18

申请号：US10942829

申请日：2004-09-17

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C7/10

CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1051

摘要： A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

摘要翻译： 一种具有数据输出电路的半导体存储器件，其使用熔丝灵活地设定驱动器强度的初始值。

公开(公告)号：US06781891B2

公开(公告)日：2004-08-24

申请号：US10349386

申请日：2003-01-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C700

CPC分类号： G05F1/10 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

摘要： The present invention relates to a half power supply voltage generating circuit and a semiconductor memory device having the same. The half power supply voltage generating circuit according to the present invention includes components that allow it to operate regardless of whether the power supply falls below a threshold voltage of included MOS transistors.

摘要翻译： 本发明涉及半电源电压产生电路和具有该半电源电压产生电路的半导体存储器件。 根据本发明的半电源电压产生电路包括允许其工作的组件，而不管电源是否低于包含的MOS晶体管的阈值电压。

公开(公告)号：US07791959B2

公开(公告)日：2010-09-07

申请号：US11708321

申请日：2007-02-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C5/14

CPC分类号： H01L23/34 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory integrated circuit device may include a first temperature sensing unit, a first voltage adjusting unit, and a MOS back bias voltage outputting unit. The first voltage adjusting unit may be configured to output a voltage based on an output signal of the temperature sensing unit such that the voltage output changes based on changes in a sensed temperature. The MOS back bias voltage outputting unit may be configured to receive the voltage output by the voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit.

摘要翻译： 存储器集成电路装置可以包括第一温度感测单元，第一电压调节单元和MOS背置偏置电压输出单元。 第一电压调整单元可以被配置为基于温度感测单元的输出信号输出电压，使得电压输出基于感测温度的变化而改变。 MOS背偏置电压输出单元可以被配置为接收由电压调节单元输出的电压，并且被配置为基于第一电压调节单元输出的电压来输出MOS反向偏置电压。

公开(公告)号：US20060023537A1

公开(公告)日：2006-02-02

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.

摘要翻译： 公开了一种半导体存储器件及其位线检测方法。 半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为 应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号 其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个 施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

公开(公告)号：US20050057983A1

公开(公告)日：2005-03-17

申请号：US10942829

申请日：2004-09-17

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C11/4096 ,  G11C7/00 ,  G11C7/10

CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1051

摘要： A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

摘要翻译： 一种具有数据输出电路的半导体存储器件，其使用熔丝灵活地设定驱动器强度的初始值。

公开(公告)号：US20080144414A1

公开(公告)日：2008-06-19

申请号：US12021762

申请日：2008-01-29

申请人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。