公开(公告)号：US6057676A

公开(公告)日：2000-05-02

申请号：US99464

申请日：1998-06-18

申请人： Ki-Jun Lee ,  Gurpreet Bhullar ,  Michael B. Vladescu

发明人： Ki-Jun Lee ,  Gurpreet Bhullar ,  Michael B. Vladescu

IPC分类号： G05F3/16 ,  G11C11/406

CPC分类号： G11C11/4074 ,  G11C11/4094 ,  G11C7/12

摘要： A regulator circuit is provided for use with cell plate voltage generators of memory cell capacitors and precharge bit lines voltage generators in semiconductor memories. The circuit employs a current source coupled to the charging reference voltage whose output is controlled by a level detector, which receives as input a reference level signal and the cell plate voltage. When the cell plate voltage drops below the reference level, the level detector triggers the current source, thereby recovering the cell plate voltage to the reference level. The level detector can be disabled through an input.

摘要翻译： 提供一种调节器电路，用于存储单元电容器的单元板电压发生器和半导体存储器中的预充电位线电压发生器。 电路采用耦合到充电参考电压的电流源，其输出由电平检测器控制，电平检测器接收参考电平信号和电池板电压作为输入。 当电池板电压低于参考电平时，电平检测器触发电流源，从而将电池板电压恢复到参考电平。 电平检测器可通过输入禁用。

公开(公告)号：US08063687B2

公开(公告)日：2011-11-22

申请号：US11833559

申请日：2007-08-03

申请人： Ki-Jun Lee ,  Gurpreet Bhullar

发明人： Ki-Jun Lee ,  Gurpreet Bhullar

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

摘要： An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

摘要翻译： 用于延迟输入时钟信号以产生输出时钟信号的模拟延迟元件。 模拟延迟元件包括用于接收输入时钟信号并响应于第一偏置电压提供中间时钟信号的延迟电路。 电流镜放大器响应于中间时钟信号在第一电流分支中产生第一电流，并响应于第一电流和第二偏置电压在第二电流分支中产生第二电流。 第二电流分支具有用于提供具有与延迟的中间时钟信号逻辑电平相对应的逻辑电平的输出时钟信号的输出节点。

公开(公告)号：US07263117B2

公开(公告)日：2007-08-28

申请号：US10409141

申请日：2003-04-09

申请人： Ki-Jun Lee ,  Gurpreet Bhullar

发明人： Ki-Jun Lee ,  Gurpreet Bhullar

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

摘要： A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

摘要翻译： 描述了包括各自具有选择性调整的粗略和微小延迟部分的模拟延迟元件的延迟线。 粗延迟部分接收输入时钟信号并产生具有基于预定粗延迟设置的斜率的斜坡信号。 精细延迟部分基于预定的精细延迟设置产生阈值电压。 比较器比较粗略延迟斜坡信号电压和精细延迟阈值电压，并且当斜坡信号电压超过精细延迟阈值电压时产生输出时钟信号。 基于32位二进制输入信号，粗略延迟是线性可调的，精细延迟是基于5位二进制输入信号进行二进制加权调整的。 粗延迟部分和精细延迟部分由延迟线控制电路控制，延迟线控制电路将输出时钟信号的反馈版本与输入时钟信号进行比较，并提供控制信号以在延迟线中增加或减少粗略和精细的延迟。

公开(公告)号：US06559699B2

公开(公告)日：2003-05-06

申请号：US09985972

申请日：2001-11-07

申请人： Ki-Jun Lee ,  Gurpreet Bhullar

发明人： Ki-Jun Lee ,  Gurpreet Bhullar

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

摘要： A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

公开(公告)号：US07349513B2

公开(公告)日：2008-03-25

申请号：US10702502

申请日：2003-11-07

申请人： Gurpreet Bhullar ,  Graham Allan

发明人： Gurpreet Bhullar ,  Graham Allan

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

摘要翻译： 一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括： 用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路 以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

公开(公告)号：US06327318B1

公开(公告)日：2001-12-04

申请号：US09106755

申请日：1998-06-30

申请人： Gurpreet Bhullar ,  Graham Allan

发明人： Gurpreet Bhullar ,  Graham Allan

IPC分类号： H03D324

CPC分类号： H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

摘要翻译： 一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括： 用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路 以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

公开(公告)号：US6075748A

公开(公告)日：2000-06-13

申请号：US399372

申请日：1999-09-20

申请人： Gurpreet Bhullar

发明人： Gurpreet Bhullar

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1018

摘要： An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation. Once the initial address of the burst operation has thusly been entered, for the remainder of the burst mode, the multiplexer selects the address loaded into the internal address master latch and operates as an edge-triggered flip/flop with the master latch accepting an incremented address in response to the falling edge of the system clock and with the slave latch loading and outputting the incremented address in response to the rising edge of the system clock. During a standby mode, circuitry is provided for disabling the counter cell and ensuring that the output nodes are stable and disabled.

摘要翻译： 描述了在同步DRAM中用于突发模式操作的地址计数器单元，其响应于系统时钟的下降沿，同时将地址输入加载到外部地址主锁存器和内部地址主锁存器中，并且还使能 多路复用器在外部和内部地址输入之间进行选择。 响应于系统时钟的后续上升沿，所选择的地址输入然后被加载到低输出负载电容从锁存器中，并进一步提供给互补输出节点。 来自一个输出节点的信号也被反馈到电路，用于在内部增加所选择的地址以在突发模式操作中保留的后续时钟周期。 一旦输入了脉冲串操作的初始地址，对于突发模式的其余部分，多路复用器选择加载到内部地址主锁存器中的地址，并作为边沿触发的触发器操作，主锁存器接受递增的 响应于系统时钟的下降沿，并且从属锁存器响应于系统时钟的上升沿而加载和输出递增的地址。 在待机模式期间，提供用于禁用计数器单元并确保输出节点稳定和禁用的电路。

公开(公告)号：US08379786B2

公开(公告)日：2013-02-19

申请号：US12984163

申请日：2011-01-04

申请人： Gurpreet Bhullar ,  Graham Allan

发明人： Gurpreet Bhullar ,  Graham Allan

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

公开(公告)号：US5991226A

公开(公告)日：1999-11-23

申请号：US995991

申请日：1997-12-22

申请人： Gurpreet Bhullar

发明人： Gurpreet Bhullar

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1018

摘要： An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation. Once the initial address of the burst operation has thusly been entered, for the remainder of the burst mode, the multiplexer selects the address loaded into the internal address master latch and operates as an edge-triggered flip/flop with the master latch accepting an incremented address in response to the falling edge of the system clock and with the slave latch loading and outputting the incremented address in response to the rising edge of the system clock. During a standby mode, circuitry is provided for disabling the counter cell and ensuring that the output nodes are stable and disabled.

公开(公告)号：US07889826B2

公开(公告)日：2011-02-15

申请号：US12026813

申请日：2008-02-06

申请人： Gurpreet Bhullar ,  Graham Allan

发明人： Gurpreet Bhullar ,  Graham Allan

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

摘要翻译： 一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括： 用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路 以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。