公开(公告)号：US20070094664A1

公开(公告)日：2007-04-26

申请号：US11256631

申请日：2005-10-21

申请人： Kimming So ,  Baobinh Truong ,  Yang Lu ,  Hon-Chong Ho ,  Li-Hung Chang ,  Chia-Cheng Choung ,  Jason Leonard

发明人： Kimming So ,  Baobinh Truong ,  Yang Lu ,  Hon-Chong Ho ,  Li-Hung Chang ,  Chia-Cheng Choung ,  Jason Leonard

IPC分类号： G06F9/46

CPC分类号： G06F9/5011 ,  G06F9/485 ,  G06F2209/5021 ,  G06F2209/507

摘要： A first thread processor of a multi-thread processor system is operable to execute a first process, and a second thread processor of the multi-thread processor system is operable to execute a second process. A control register is operable to store priority information that is individually associated with at least one of the first thread processor and the second thread processor. The priority information identifies a prioritization of the first thread processor and/or a restriction on the second thread processor in a use of a shared hardware resource during execution of at least one of the first process and the second process.

摘要翻译： 多线程处理器系统的第一线程处理器可操作以执行第一进程，并且多线程处理器系统的第二线程处理器可操作以执行第二进程。 控制寄存器可操作以存储与第一线程处理器和第二线程处理器中的至少一个单独关联的优先级信息。 在执行第一进程和第二进程中的至少一个时，优先级信息在使用共享硬件资源时识别第一线程处理器的优先级和/或对第二线程处理器的限制。

公开(公告)号：US07971043B2

公开(公告)日：2011-06-28

申请号：US11944416

申请日：2007-11-22

申请人： Li-Hung Chang ,  Hong-Men Su

发明人： Li-Hung Chang ,  Hong-Men Su

IPC分类号： G06F9/38 ,  G06F15/76

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3869 ,  G06F9/3873

摘要： An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.

摘要翻译： 电子系统包括具有串联耦合的第一数量的流水线级的流水线，流水线控制单元和逻辑引擎，其中流水线中的每个流水线级用于在时钟信号的每个周期将数据输出到下一流水线级 。 流水线控制单元用于将流水线中的第一数量的流水线级改变为第二数量的流水线级。 该逻辑引擎用于利用具有第一数量的流水线级的流水线以第一模式执行电子系统的操作，并且通过利用具有第二数量的流水线级的管线，以第二模式执行电子系统的操作。 耦合到管道和逻辑引擎的频率控制单元和电压控制单元分别相应地调整电子系统的频率和电压。

公开(公告)号：US20090138674A1

公开(公告)日：2009-05-28

申请号：US11944416

申请日：2007-11-22

申请人： Li-Hung Chang ,  Hong-Men Su

发明人： Li-Hung Chang ,  Hong-Men Su

IPC分类号： G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3869 ,  G06F9/3873

摘要： An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.

摘要翻译： 电子系统包括具有串联耦合的第一数量的流水线级的流水线，流水线控制单元和逻辑引擎，其中流水线中的每个流水线级用于在时钟信号的每个周期将数据输出到下一流水线级 。 流水线控制单元用于将流水线中的第一数量的流水线级改变为第二数量的流水线级。 该逻辑引擎用于利用具有第一数量的流水线级的流水线以第一模式执行电子系统的操作，并且通过利用具有第二数量的流水线级的管线，以第二模式执行电子系统的操作。 耦合到管道和逻辑引擎的频率控制单元和电压控制单元分别相应地调整电子系统的频率和电压。

公开(公告)号：US20080301480A1

公开(公告)日：2008-12-04

申请号：US11757411

申请日：2007-06-04

申请人： Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

发明人： Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

IPC分类号： G06F1/28 ,  G06F9/46

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.

摘要翻译： 提供了一种用于控制其处理器的计算机系统和方法。 处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。 然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。 最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。 因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。

公开(公告)号：US07822999B2

公开(公告)日：2010-10-26

申请号：US11757411

申请日：2007-06-04

申请人： Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

发明人： Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

IPC分类号： G06F1/00 ,  G06F1/26 ,  G11C5/14 ,  H04B1/38

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.

摘要翻译： 提供了一种用于控制其处理器的计算机系统和方法。 处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。 然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。 最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。 因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。