公开(公告)号：US06259162B1

公开(公告)日：2001-07-10

申请号：US09150628

申请日：1998-09-09

申请人： Kin F. Ma ,  Eric T. Stubbs

发明人： Kin F. Ma ,  Eric T. Stubbs

IPC分类号： H01L2940

CPC分类号： H01L21/76838 ,  Y10S257/907

摘要： An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

摘要翻译： 本发明的一个实施例公开了一种具有排列成互补对的数字线的阵列的存储器件，该阵列包括： 其中具有沟槽的基本平坦的层; 至少部分驻留在沟槽中的第一级数字线; 驻留在层的表面上的第二级数字线，第二级与第一级的数字线大致平行地延伸。 数字线的第一级与第二级数字线处于交替位置，并且交替位置包括与第二级相邻的第二互补数字线对的第一级处的第一互补数字线对的重复图案。

公开(公告)号：US06570258B2

公开(公告)日：2003-05-27

申请号：US09884630

申请日：2001-06-18

申请人： Kin F. Ma ,  Eric T. Stubbs

发明人： Kin F. Ma ,  Eric T. Stubbs

IPC分类号： H01L2940

CPC分类号： H01L21/76838 ,  Y10S257/907

摘要： An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

摘要翻译： 本发明的一个实施例公开了一种具有排列成互补对的数字线的阵列的存储器件，该阵列包括： 其中具有沟槽的基本平坦的层; 至少部分驻留在沟槽中的第一级数字线; 驻留在层的表面上的第二级数字线，第二级与第一级的数字线大致平行地延伸。 数字线的第一级与第二级数字线处于交替位置，并且交替位置包括与第二级相邻的第二互补数字线对的第一级处的第一互补数字线对的重复图案。

公开(公告)号：US5854128A

公开(公告)日：1998-12-29

申请号：US641154

申请日：1996-04-29

申请人： Kin F. Ma ,  Eric T. Stubbs

发明人： Kin F. Ma ,  Eric T. Stubbs

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  Y10S257/907

摘要： An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

公开(公告)号：US06309975B1

公开(公告)日：2001-10-30

申请号：US08818660

申请日：1997-03-14

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material. One preferred selective etching process uses an etchant solution comprising a selected weight percentage of tetramethyl ammonium hydroxide in deionized water. The etchant solution etches relatively unimplanted silicon-containing material implanted up to 60 times faster than it etches silicon-containing material implanted to beyond a threshold concentration of ions. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

摘要翻译： 公开了用于通过离子注入形成含硅材料的成形结构的方法，以及对注入一定浓度的离子的含硅材料或对相对未被植入的含硅材料选择性的蚀刻工艺是选择性的蚀刻工艺。 通常，该方法最初涉及在半导体衬底上提供诸如多晶硅或外延硅的含硅材料层。 然后掩蔽含硅材料层，并将离子注入含硅材料层的暴露部分。 去除掩模，并且进行上述选择性蚀刻工艺以导致被蚀刻掉的含硅材料层的注入和相对未被注入的部分中的一个，而另一个放置形成含硅的成形结构 材料。 一种优选的选择性蚀刻方法使用包含选定重量百分比的四甲基氢氧化铵在去离子水中的蚀刻剂溶液。 蚀刻剂溶液蚀刻相对未被植入的含硅材料，其比注入超过阈值浓度离子的含硅材料蚀刻高达60倍。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

公开(公告)号：US06596648B2

公开(公告)日：2003-07-22

申请号：US10193850

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06599840B2

公开(公告)日：2003-07-29

申请号：US10194833

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06596642B2

公开(公告)日：2003-07-22

申请号：US10193801

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06461967B2

公开(公告)日：2002-10-08

申请号：US09907296

申请日：2001-07-16

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

公开(公告)号：US06261964B1

公开(公告)日：2001-07-17

申请号：US09205989

申请日：1998-12-04

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。