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    Material removal method for forming a structure
    3.
    发明授权
    Material removal method for forming a structure 有权
    用于形成结构的材料去除方法

    公开(公告)号：US06461967B2

    公开(公告)日：2002-10-08

    申请号：US09907296

    申请日：2001-07-16

    申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    IPC分类号： H01L2100

    CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

    摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

    摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

    Material removal method for forming a structure
    4.
    发明授权
    Material removal method for forming a structure 有权
    用于形成结构的材料去除方法

    公开(公告)号：US06261964B1

    公开(公告)日：2001-07-17

    申请号：US09205989

    申请日：1998-12-04

    申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    IPC分类号： H01L2100

    CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

    摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

    摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

    Methods of making implanted structures
    5.
    发明授权
    Methods of making implanted structures 失效
    植入结构的方法

    公开(公告)号：US06309975B1

    公开(公告)日：2001-10-30

    申请号：US08818660

    申请日：1997-03-14

    申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

    IPC分类号： H01L2100

    CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

    摘要： Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material. One preferred selective etching process uses an etchant solution comprising a selected weight percentage of tetramethyl ammonium hydroxide in deionized water. The etchant solution etches relatively unimplanted silicon-containing material implanted up to 60 times faster than it etches silicon-containing material implanted to beyond a threshold concentration of ions. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

    摘要翻译： 公开了用于通过离子注入形成含硅材料的成形结构的方法，以及对注入一定浓度的离子的含硅材料或对相对未被植入的含硅材料选择性的蚀刻工艺是选择性的蚀刻工艺。 通常，该方法最初涉及在半导体衬底上提供诸如多晶硅或外延硅的含硅材料层。 然后掩蔽含硅材料层，并将离子注入含硅材料层的暴露部分。 去除掩模，并且进行上述选择性蚀刻工艺以导致被蚀刻掉的含硅材料层的注入和相对未被注入的部分中的一个，而另一个放置形成含硅的成形结构 材料。 一种优选的选择性蚀刻方法使用包含选定重量百分比的四甲基氢氧化铵在去离子水中的蚀刻剂溶液。 蚀刻剂溶液蚀刻相对未被植入的含硅材料，其比注入超过阈值浓度离子的含硅材料蚀刻高达60倍。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

    Method to protect gate stack material during source/drain reoxidation
    7.
    发明授权
    Method to protect gate stack material during source/drain reoxidation 失效
    在源/排放再氧化过程中保护栅堆叠材料的方法

    公开(公告)号：US05998290A

    公开(公告)日：1999-12-07

    申请号：US097353

    申请日：1998-06-15

    申请人： Zhiqiang Wu ,  Pai-Hung Pan

    发明人： Zhiqiang Wu ,  Pai-Hung Pan

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205

    CPC分类号： H01L21/28061 ,  H01L29/4941 ,  H01L29/4983 ,  H01L21/32137 ,  Y10S257/90 ,  Y10S257/915

    摘要： A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

    摘要翻译： 制造栅极堆叠的工艺，由此保持栅极侧壁和衬底表面的完整性。 氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。 这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。 在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。

    Gate stack with improved sidewall integrity
    8.
    发明授权
    Gate stack with improved sidewall integrity 失效
    具有改进的侧壁完整性的门叠层

    公开(公告)号：US5925918A

    公开(公告)日：1999-07-20

    申请号：US902808

    申请日：1997-07-30

    申请人： Zhiqiang Wu ,  Pai-Hung Pan

    发明人： Zhiqiang Wu ,  Pai-Hung Pan

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L21/28061 ,  H01L29/4941 ,  H01L29/4983 ,  H01L21/32137 ,  Y10S257/90 ,  Y10S257/915

    摘要： A process of manufacturing a gate stack is disclosed whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

    摘要翻译： 公开了一种制造栅极堆叠的工艺，由此保持了栅极侧壁和基板表面的完整性。 氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。 这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。 在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。

    Semiconductor devices having gate stack with improved sidewall integrity
    9.
    发明授权
    Semiconductor devices having gate stack with improved sidewall integrity 有权
    具有具有改进的侧壁完整性的栅极叠层的半导体器件

    公开(公告)号：US6075274A

    公开(公告)日：2000-06-13

    申请号：US323178

    申请日：1999-05-28

    申请人： Zhiqiang Wu ,  Pai-Hung Pan

    发明人： Zhiqiang Wu ,  Pai-Hung Pan

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L21/28061 ,  H01L29/4941 ,  H01L29/4983 ,  H01L21/32137 ,  Y10S257/90 ,  Y10S257/915

    摘要： A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

    摘要翻译： 制造栅极堆叠的工艺，由此保持栅极侧壁和衬底表面的完整性。 氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。 这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。 在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。