公开(公告)号：US20130001681A1

公开(公告)日：2013-01-03

申请号：US13634603

申请日：2010-05-27

申请人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

发明人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/7813

摘要： A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

摘要翻译： 在形成沟槽（7）之前，用于形成n +源极层（11）的掩模由衬底的表面上的氮化物膜形成。 此时，确保衬底表面上的n +源层（11）的足够的宽度。 由此，得到n +源极层（11）与源电极（15）之间的稳定的接触。 在作为嵌入沟槽（7）中的栅电极（10a）的掺杂多晶硅上形成作为0.1微米以上且0.3微米以下的厚度的层间绝缘膜的CVD氧化膜（12） ，并且在CVD氧化膜（12）上形成未被氧化的未掺杂多晶硅（13）。 由此，抑制CVD氧化膜（12）中的空隙的产生，并且通过不氧化非掺杂多晶硅（13），容易制造半导体装置。

公开(公告)号：US09553185B2

公开(公告)日：2017-01-24

申请号：US13634603

申请日：2010-05-27

申请人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

发明人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L29/08

CPC分类号： H01L29/66734 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/7813

摘要： A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

摘要翻译： 在形成沟槽（7）之前，用于形成n +源极层（11）的掩模由衬底的表面上的氮化物膜形成。 此时，确保衬底表面上的n +源层（11）的足够的宽度。 由此，得到n +源极层（11）与源电极（15）之间的稳定的接触。 在作为嵌入沟槽（7）中的栅电极（10a）的掺杂多晶硅上形成作为0.1微米以上且0.3微米以下的厚度的层间绝缘膜的CVD氧化膜（12） ，并且在CVD氧化膜（12）上形成未被氧化的未掺杂多晶硅（13）。 由此，抑制CVD氧化膜（12）中的空隙的产生，并且通过不氧化非掺杂多晶硅（13），容易制造半导体装置。

公开(公告)号：US20120315770A1

公开(公告)日：2012-12-13

申请号：US13476273

申请日：2012-05-21

申请人： Hiroshi Nakashima ,  Haigui Yang ,  Hitoshi Sumida

发明人： Hiroshi Nakashima ,  Haigui Yang ,  Hitoshi Sumida

IPC分类号： H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7802

摘要： A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.

摘要翻译： 根据本发明的制造半导体器件的方法包括清洗碳化硅衬底1表面的步骤S1，将材料气体引入等离子体中并将原料气体中包含的原子照射到碳化硅衬底1上的步骤S2， 在碳化硅衬底1上生长氮化硅膜2，通过ECR等离子体CVD法在氮化硅膜2上沉积氧化硅膜3的步骤S3和退火包括氮化硅膜2和氧化硅的碳化硅衬底1的步骤S4 在氮气氛下形成薄膜3。 通过制造根据本发明的半导体器件的方法，获得了具有包括界面态密度和平带电压的优异界面特性的半导体器件。

公开(公告)号：US08014118B2

公开(公告)日：2011-09-06

申请号：US12071690

申请日：2008-02-25

申请人： Koji Ikegami ,  Hideto Kobayashi ,  Hitoshi Sumida ,  Hiroshi Shimabukuro

发明人： Koji Ikegami ,  Hideto Kobayashi ,  Hitoshi Sumida ,  Hiroshi Shimabukuro

IPC分类号： H02H9/00

CPC分类号： G09G3/296 ,  G09G2330/04

摘要： A load driving circuit in which a load is connected to the connecting point of transistors as low-side and high-side main switch elements that have a totem pole structure and are connected between a pair of drive voltage supply lines. A protection circuit section is provided for the high-side transistor. In the protection circuit section, a resistor as a voltage control element is provided for a MOSFET as an overvoltage prevention switch and a capacitor is connected between the gate and the drain of the MOSFET.

摘要翻译： 一种负载驱动电路，其中负载连接到晶体管的连接点，作为具有图腾柱结构并连接在一对驱动电压电源线之间的低侧和高侧主开关元件。 为高侧晶体管提供保护电路部分。 在保护电路部分中，为MOSFET提供作为电压控制元件的电阻器作为过电压防止开关，并且在MOSFET的栅极和漏极之间连接电容器。

公开(公告)号：US20060050455A1

公开(公告)日：2006-03-09

申请号：US11219796

申请日：2005-09-07

申请人： Hitoshi Sumida ,  Akinobu Teramoto ,  Ken-ichi Nonaka ,  Toshio Naka

发明人： Hitoshi Sumida ,  Akinobu Teramoto ,  Ken-ichi Nonaka ,  Toshio Naka

IPC分类号： H02H9/00

CPC分类号： H02P27/06 ,  B60L3/003 ,  B60L2210/20 ,  H02M7/003 ,  Y02T10/725

摘要： A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.

公开(公告)号：US5572055A

公开(公告)日：1996-11-05

申请号：US491517

申请日：1995-06-19

申请人： Hitoshi Sumida

发明人： Hitoshi Sumida

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76 ,  H01L29/74 ,  H01L29/94

CPC分类号： H01L29/0696 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7398

摘要： An insulated-gate bipolar transistor includes a semiconductor region of a first conductive type; a base layer of a second conductive type diffused from a surface of the semiconductor region; a source layer of the first conductive type diffused in a surface portion of the base layer; an insulated gate buried in a recess dug from the surface of the source layer through the base layer up to the semiconductor region; a collector layer of the second conductive type diffused from a surface of the semiconductor region on an opposite side of the insulated gate with respect to the source layer; an emitter terminal drawn from the base layer and the source layer; a collector terminal drawn from the collector layer; and a gate terminal drawn from the insulated gate.

摘要翻译： 绝缘栅双极晶体管包括第一导电类型的半导体区域; 从所述半导体区域的表面扩散的第二导电类型的基底层; 所述第一导电类型的源极层扩散在所述基底层的表面部分中; 埋置在从源极层的表面穿过基底层直到半导体区域的凹部中的绝缘栅极; 所述第二导电类型的集电极层相对于所述源极层从所述绝缘栅极的相对侧上的所述半导体区域的表面扩散; 从基层和源层绘制的发射极端子; 从集电极层抽出的集电极端子; 以及从绝缘栅极拉出的栅极端子。

公开(公告)号：US08405343B2

公开(公告)日：2013-03-26

申请号：US13111122

申请日：2011-05-19

申请人： Hitoshi Sumida ,  Akinobu Teramoto ,  Ken-ichi Nonaka ,  Toshio Naka

发明人： Hitoshi Sumida ,  Akinobu Teramoto ,  Ken-ichi Nonaka ,  Toshio Naka

IPC分类号： H02P27/04

CPC分类号： H02P27/06 ,  B60L3/003 ,  B60L2210/20 ,  H02M7/003 ,  Y02T10/725

摘要： A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.

摘要翻译： 一个小型化，低成本的高可靠性逆变器单元。 控制电路部分，用于控制包括在逆变器电路部分中的高击穿电压半导体元件的操作定时;以及第一和第二驱动和异常检测电路部分，用于根据操作时间输出用于驱动高击穿电压半导体元件的驱动信号， 将逆变器电路部分的异常返回到控制电路部分形成在作为一个集成电路芯片的SOI衬底上。 在集成电路芯片上，参考电位不同的电路形成区域通过电介质彼此分离。 形成用于传输由电介质分离的电路形成区域之间交换的信号的多个电平移位器。

公开(公告)号：US20080203926A1

公开(公告)日：2008-08-28

申请号：US12071690

申请日：2008-02-25

申请人： Koji Ikegami ,  Hideto Kobayashi ,  Hitoshi Sumida ,  Hiroshi Shimabukuro

发明人： Koji Ikegami ,  Hideto Kobayashi ,  Hitoshi Sumida ,  Hiroshi Shimabukuro

IPC分类号： H05B41/36

CPC分类号： G09G3/296 ,  G09G2330/04

摘要： A load driving circuit in which a load is connected to the connecting point of transistors as low-side and high-side main switch elements that have a totem pole structure and are connected between a pair of drive voltage supply lines. A protection circuit section is provided for the high-side transistor. In the protection circuit section, a resistor as a voltage control element is provided for a MOSFET as an overvoltage prevention switch and a capacitor is connected between the gate and the drain of the MOSFET.

摘要翻译： 一种负载驱动电路，其中负载连接到晶体管的连接点，作为具有图腾柱结构并连接在一对驱动电压电源线之间的低侧和高侧主开关元件。 为高侧晶体管提供保护电路部分。 在保护电路部分中，为MOSFET提供作为电压控制元件的电阻器作为过电压防止开关，并且在MOSFET的栅极和漏极之间连接电容器。

公开(公告)号：US06441432B1

公开(公告)日：2002-08-27

申请号：US09442023

申请日：1999-11-17

申请人： Hitoshi Sumida

发明人： Hitoshi Sumida

IPC分类号： H01L2976

CPC分类号： H01L29/7824 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/7816

摘要： A high voltage lateral semiconductor device is provided in which an n buffer region (14) surrounds an n+ drain region (11), and an n drift region (3) surrounds the n buffer region (14), while a p well region (44) surrounds the n drift region (3). No n+ source region is formed in a circular arc portion (47) of the p well region (44), but an n+ source region (46) is formed in each straight portion (48) of the p well region (44). A p+ contact region (45) surrounds the p well region (44) and the n+ source region (46). A gate oxide film is formed on a part of the n+ source region (46) located close to the n drift region, and on the p well region (44) and the outer peripheral portion of the n drill region (3), and a gate electrode is formed on the gate oxide film.

摘要翻译： 提供一种高电压横向半导体器件，其中n缓冲区域围绕n +漏极区域，并且n漂移区域围绕n缓冲区域，而p阱区域（44） 围绕n漂移区域（3）。 在p阱区（44）的圆弧部（47）中不形成n +源极区，但是在p阱区（44）的每个直线部（48）中形成n +源极区（46）。 p +接触区域（45）围绕p阱区域（44）和n +源极区域（46）。 栅极氧化膜形成在位于n漂移区附近的n +源极区域（46）的一部分上，在p阱区域（44）和n钻孔区域（3）的外周部分上形成， 栅电极形成在栅氧化膜上。

公开(公告)号：US5624855A

公开(公告)日：1997-04-29

申请号：US491686

申请日：1995-06-19

申请人： Hitoshi Sumida

发明人： Hitoshi Sumida

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7398

摘要： An insulated-gate bipolar transistor includes a semiconductor region of a first conductive type; a base layer of a second conductive type diffused from a surface of the semiconductor region; a source layer of the first conductive type diffused in a surface portion of the base layer; an insulated gate buried in a recess dug from the surface of the source layer through the base layer up to the semiconductor region; a collector layer of the second conductive type diffused from a surface of the semiconductor region on an opposite side of the insulated gate with respect to the source layer; an emitter terminal drawn from the base layer and the source layer; a collector terminal drawn from the collector layer; and a gate terminal drawn from the insulated gate.

摘要翻译： 绝缘栅双极晶体管包括第一导电类型的半导体区域; 从所述半导体区域的表面扩散的第二导电类型的基底层; 所述第一导电类型的源极层扩散在所述基底层的表面部分中; 埋置在从源极层的表面穿过基底层直到半导体区域的凹部中的绝缘栅极; 所述第二导电类型的集电极层相对于所述源极层从所述绝缘栅极的相对侧上的所述半导体区域的表面扩散; 从基层和源层绘制的发射极端子; 从集电极层抽出的集电极端子; 以及从绝缘栅极拉出的栅极端子。