公开(公告)号：US09768291B2

公开(公告)日：2017-09-19

申请号：US15196838

申请日：2016-06-29

申请人： Infineon Technologies Austria AG

发明人： Franz Hirler

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/40 ,  H01L29/66 ,  H01L29/73 ,  H01L29/739 ,  H01L21/266

CPC分类号： H01L29/7811 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/8611

摘要： A semiconductor device includes a plurality of compensation regions of a vertical electrical element arrangement, a plurality of drift regions of the vertical electrical element arrangement and a non-depletable doping region. The compensation regions of the plurality of compensation regions are arranged in a semiconductor substrate of the semiconductor device. Further, the plurality of drift regions of the vertical electrical element arrangement are arranged in the semiconductor substrate within a cell region of the semiconductor device. The plurality of drift regions and the plurality of compensation regions are arranged alternatingly in a lateral direction. The non-depletable doping region extends laterally from an edge of the cell region towards an edge of the semiconductor substrate. The non-depletable doping region has a doping non-depletable by voltages applied to the semiconductor device during blocking operation.

公开(公告)号：US09704954B2

公开(公告)日：2017-07-11

申请号：US15041671

申请日：2016-02-11

申请人： Infineon Technologies Austria AG

发明人： Daniel Tutuc ,  Franz Hirler ,  Andreas Voerckel ,  Hans Weber

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/0696 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/417 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7398 ,  H01L29/7823

摘要： A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region.

公开(公告)号：US20170179266A1

公开(公告)日：2017-06-22

申请号：US15447692

申请日：2017-03-02

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： HIROYUKI TANAKA

IPC分类号： H01L29/739 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7394 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7398

摘要： A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

公开(公告)号：US20160379936A1

公开(公告)日：2016-12-29

申请号：US15121419

申请日：2015-02-27

申请人： LFOUNDRY S.R.L.

发明人： Gerhard Spitzlsperger ,  Carsten Schmidt

IPC分类号： H01L23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L21/74 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/562 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823418 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/43 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/808 ,  H01L2224/4502

摘要： A method of fabricating a semiconductor product includes processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface of the wafer. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes forming implantations from the backside of the wafer, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.

摘要翻译： 一种制造半导体产品的方法包括从前表面处理半导体晶片，所述前表面包括设置在与所述前表面相邻的所述晶片的所述基板中的结构，并且形成嵌入在所述晶片的前表面上的电介质层中的布线。 晶片在其前表面安装到载体晶片，使得可以从晶片的背面去除材料以使半导体晶片变薄。 半导体晶片的背面处理包括从晶片的背面形成注入，形成深沟槽以将结构与晶片内的其它结构隔离，形成通硅通孔以接触晶片前侧的特征，并形成主体 联系。 可以在同一晶片内产生多个器件。

公开(公告)号：US09490352B2

公开(公告)日：2016-11-08

申请号：US15074633

申请日：2016-03-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC分类号： H01L29/735 ,  H01L29/08 ,  H01L27/06 ,  H01L29/10 ,  H01L29/167

CPC分类号： H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

摘要： A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

摘要翻译： 用于形成双极结型晶体管的方法包括在集电极本征区域和发射极本征区域之间形成集电极本征区域，发射极本征区域和本征基极区域。 集电体外部接触区域与集电极本征区域直接接触形成; 在发射极本征区域上形成发射极外部接触区域，并且形成与本征基极区域直接接触的基本非本征接触区域。 将碳引入到集电体外部本征接触区域，发射极非本征接触区域和基本非本征接触区域中的至少一个中，以抑制掺杂剂扩散到接合区域中。

公开(公告)号：US20160293744A1

公开(公告)日：2016-10-06

申请号：US15081176

申请日：2016-03-25

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： HIROYUKI TANAKA

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7394 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7398

摘要： A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

摘要翻译： 一种半导体器件，包括：设置有P型基极区域; 设置在P型基区内的N型发射极区域; 设置在所述N型半导体层的表层部分并与所述P型基极区分离的P型集电极区域; 栅极绝缘膜，其设置在所述N型半导体层的表面上，并且与所述P型基极区域和所述N型发射极区域接触; 栅极绝缘膜上的栅电极; 在P型基极区域和P型集电极区域之间设置在N型半导体层的内部的柱状结构体，其中，柱状结构的一端与延伸到表面层部分的N型半导体连接 并且柱状结构包括在N型半导体层的深度方向上延伸的绝缘体。

公开(公告)号：US07989921B2

公开(公告)日：2011-08-02

申请号：US11629022

申请日：2005-06-10

申请人： Ralf Lerner

发明人： Ralf Lerner

IPC分类号： H01L31/11 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC分类号： H01L29/7398 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/861

摘要： An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

摘要翻译： SOI器件包括限定垂直漂移区的隔离沟槽，隔离沟槽所延伸的掩埋绝缘层，以及用于发射邻近绝缘层形成并与漂移区接触的电荷载流子的电极区域。 电极区域包括具有第一类型掺杂的第一条形部分和具有与第一类型掺杂相反的第二类型掺杂的第二条形部分。 在隔离沟槽的第一侧壁处提供第一类型掺杂的第一侧壁掺杂，并且在隔离沟槽的第二侧壁处提供第二类型的掺杂的第二侧壁掺杂。 第一条形部分与第一侧壁掺杂接触，第二条形部分与第二侧壁掺杂接触。

公开(公告)号：US06439514B1

公开(公告)日：2002-08-27

申请号：US09493937

申请日：2000-01-28

申请人： Hitoshi Yamaguchi ,  Yoshitaka Noda

发明人： Hitoshi Yamaguchi ,  Yoshitaka Noda

IPC分类号： H01L2900

CPC分类号： H01L29/41758 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398 ,  H01L29/7824

摘要： Pch-MOS transistors to which a power supply potential is applied are respectively surrounded by first trenches, and Nch-MOS transistors to which a ground potential is applied are respectively surrounded by second trenches. The first trenches are surrounded by a third trench, and the second trenches are surrounded by a fourth trench. A silicon layer existing inside the third trench is set at the power source potential. The silicon layer existing between the third and fourth trenches are set at a floating state. Accordingly, each thickness of oxide layers filling the trenches can be reduced.

摘要翻译： 施加电源电位的Pch-MOS晶体管分别被第一沟槽环绕，并且施加有接地电位的Nch-MOS晶体管分别被第二沟槽包围。 第一沟槽被第三沟槽围绕，第二沟槽被第四沟槽围绕。 存在于第三沟槽内的硅层设置在电源电位。 存在于第三沟槽和第四沟槽之间的硅层被设置为浮置状态。 因此，可以减少填充沟槽的氧化物层的每个厚度。

公开(公告)号：US5920087A

公开(公告)日：1999-07-06

申请号：US970103

申请日：1997-11-13

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

摘要翻译： 子栅电极配置成通过栅极绝缘膜与介于第一n型源极层和n型漂移层之间的第一p型基极层的表面和 第二p型基极层，其介于第二n型源极层和n型漂移层之间并且面向第一p型基极层。 主栅极布置成通过栅极绝缘膜面对介于第二n型源极层和n型漂移层之间的第二p型基极层的表面，并且不面向第一p 型基层。 构造三个n型MOSFET，使得在第一p型基极层中形成一个n型沟道，并且在第二p型基极层中形成两个n型沟道。 要形成三个通道，从而有效地扩大通道宽度，增加电流密度。 第二p型基层在漂移方向上的长度为10μm以下。

公开(公告)号：US5796125A

公开(公告)日：1998-08-18

申请号：US528570

申请日：1995-09-15

申请人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76 ,  H01L29/94 ,  H01L31/111

CPC分类号： H01L29/0696 ,  H01L29/7394 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7824 ,  H01L29/4238

摘要： A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.

摘要翻译： 高耐压半导体器件。 该器件包括半导体衬底，形成在半导体衬底上的绝缘膜，形成在绝缘膜上的有源区，形成在有源区的表面部分中的漏极和基极区以及形成在有源区的表面部分中的源极区 基地区。 第一和第二栅极绝缘膜形成在穿过基极区域的第一和第二沟槽的内表面上，以便与源极区域接触并到达有源区域，第一和第二电极被埋在第一和第二沟槽中。 由栅极绝缘膜，栅极电极，源极区域，基极区域和有源区域构成的MOS结构中形成有两个以上的沟道区域。