公开(公告)号：US20240070062A1

公开(公告)日：2024-02-29

申请号：US18502498

申请日：2023-11-06

申请人： Kioxia Corporation

发明人： Daisuke IWAI ,  Toshio FUJISAWA ,  Keigo HARA

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/403 ,  G06F2212/7205

摘要： According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US20220066921A1

公开(公告)日：2022-03-03

申请号：US17184313

申请日：2021-02-24

申请人： KIOXIA CORPORATION

发明人： Daisuke IWAI ,  Toshio FUJISAWA ,  Keigo HARA

IPC分类号： G06F12/02 ,  G06F12/06

摘要： According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US20210064524A1

公开(公告)日：2021-03-04

申请号：US16806173

申请日：2020-03-02

申请人： KIOXIA CORPORATION

发明人： Keiri NAKANISHI ,  Konosuke WATANABE ,  Kohei OIKAWA ,  Daisuke IWAI

IPC分类号： G06F12/02 ,  G06F13/16 ,  G11C16/34 ,  G11C16/10

摘要： A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.