MEMORY DEVICE
    1.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20240265984A1

    公开(公告)日:2024-08-08

    申请号:US18432269

    申请日:2024-02-05

    CPC classification number: G11C16/3459 G11C16/102 G11C16/26

    Abstract: According to one embodiment, a memory device includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or larger). The sequencer is configured to execute a write operation having a loop process including a program operation and a verify operation. The program operation includes a first program process and a second program process. The sequencer is further configured to cause the first memory cell to store data by either the first program process or the second program process according to data to be written into the first memory cell in the write operation.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请

    公开(公告)号:US20250124989A1

    公开(公告)日:2025-04-17

    申请号:US18814679

    申请日:2024-08-26

    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请

    公开(公告)号:US20220084609A1

    公开(公告)日:2022-03-17

    申请号:US17201332

    申请日:2021-03-15

    Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

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