公开(公告)号：US20220093636A1

公开(公告)日：2022-03-24

申请号：US17199660

申请日：2021-03-12

Applicant: KIOXIA CORPORATION

Inventor： Toshiya MURAKAMI ,  Kenji TASHIRO ,  Hidenori MIYAGAWA ,  Reiko KITAMURA

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.

公开(公告)号：US20240315026A1

公开(公告)日：2024-09-19

申请号：US18599913

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Ayumi WATARAI ,  Kenji TASHIRO ,  Kosei NODA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: According to one embodiment, in a semiconductor storage device, a plurality of second pillars each includes a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of a stacked body and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar. The second sub-pillar includes a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body, a second insulating layer covering a sidewall of the semiconductor layer, a third insulating layer covering a sidewall of the second insulating layer, and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.

公开(公告)号：US20230086773A1

公开(公告)日：2023-03-23

申请号：US17693617

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Akira YOTSUMOTO ,  Keisuke SUDA ,  Kenji TASHIRO ,  Tetsuya YAMASHITA ,  Daigo ICHINOSE

IPC: H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction; and first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the dummy region, each of the first and second plate-like portions dividing the stacked body excluding at least a part of the end portion of the dummy region in the second direction.