公开(公告)号：US11765916B2

公开(公告)日：2023-09-19

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US12069872B2

公开(公告)日：2024-08-20

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US11985834B2

公开(公告)日：2024-05-14

申请号：US17346478

申请日：2021-06-14

Applicant: Kioxia Corporation

Inventor： Yoshiki Kamata ,  Misako Morota ,  Yukihiro Nomura ,  Yoshiaki Asao

IPC: H10B63/00 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B53/30 ,  H10B63/34

Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

公开(公告)号：US11948636B2

公开(公告)日：2024-04-02

申请号：US17693935

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yoshiki Kamata ,  Yoshiaki Asao ,  Yukihiro Nomura ,  Misako Morota ,  Daisaburo Takashima ,  Takahiko Iizuka ,  Shigeru Kawanaka

IPC: G11C13/00 ,  G11C5/06 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0069 ,  G11C5/06 ,  H10B63/30 ,  H10N70/826 ,  G11C2013/0078 ,  G11C2213/75

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.