公开(公告)号：US20210174878A1

公开(公告)日：2021-06-10

申请号：US17181998

申请日：2021-02-22

Applicant: KIOXIA CORPORATION

Inventor： Naoya TOKIWA

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

公开(公告)号：US20230134753A1

公开(公告)日：2023-05-04

申请号：US18148022

申请日：2022-12-29

Applicant: Kioxia Corporation

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

公开(公告)号：US20240296893A1

公开(公告)日：2024-09-05

申请号：US18662971

申请日：2024-05-13

Applicant: Kioxia Corporation

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

公开(公告)号：US20230377659A1

公开(公告)日：2023-11-23

申请号：US18359764

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/0466 ,  G11C16/08

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

公开(公告)号：US20210358555A1

公开(公告)日：2021-11-18

申请号：US17387765

申请日：2021-07-28

Applicant: KIOXIA CORPORATION

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

公开(公告)号：US20230213993A1

公开(公告)日：2023-07-06

申请号：US18181488

申请日：2023-03-09

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Yasuhiro HIRASHIMA ,  Naoya TOKIWA

IPC: G06F1/28

CPC classification number: G06F1/28 ,  G11C16/0483

Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

公开(公告)号：US20200342941A1

公开(公告)日：2020-10-29

申请号：US16802446

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Naoya TOKIWA

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

公开(公告)号：US20230118624A1

公开(公告)日：2023-04-20

申请号：US18071470

申请日：2022-11-29

Applicant: KIOXIA CORPORATION

Inventor： Naoya TOKIWA

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

公开(公告)号：US20200126626A1

公开(公告)日：2020-04-23

申请号：US16719585

申请日：2019-12-18

Applicant: KIOXIA Corporation

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.