公开(公告)号：US20240244839A1

公开(公告)日：2024-07-18

申请号：US18435113

申请日：2024-02-07

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Shingo NAKAZAWA

IPC: H10B41/35 ,  H10B41/27 ,  H10B41/47

CPC classification number: H10B41/35 ,  H10B41/27 ,  H10B41/47

Abstract: A memory system for low power consumption and high speed read operation in the memory system includes a source line, a string select line having i layers, a first word line having i layers, a second word line having i layers, a select gate line having 1 layer which is divided into 2n, a plurality of memory pillars and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string includes a first transistor, i first memory cells and j second memory cells. The first transistor, the i first memory cells, and the j second memory cells are electrically connected in series. The second string includes a second transistor, i third memory cells, and j fourth memory cells. The second transistor, the i third memory cells, and the j fourth memory cells are electrically connected in series.

公开(公告)号：US20240096429A1

公开(公告)日：2024-03-21

申请号：US18458071

申请日：2023-08-29

Applicant: Kioxia Corporation

Inventor： Shingo NAKAZAWA ,  Yuki INUZUKA

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.

公开(公告)号：US20220310175A1

公开(公告)日：2022-09-29

申请号：US17467815

申请日：2021-09-07

Applicant: Kioxia Corporation

Inventor： Shingo NAKAZAWA

IPC: G11C16/26 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/48 ,  G11C16/30

Abstract: A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.

公开(公告)号：US20220084608A1

公开(公告)日：2022-03-17

申请号：US17199718

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Shingo NAKAZAWA ,  Takashi MAEDA

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.

公开(公告)号：US20220406384A1

公开(公告)日：2022-12-22

申请号：US17643726

申请日：2021-12-10

Applicant: KIOXIA CORPORATION

Inventor： Shingo NAKAZAWA

IPC: G11C16/16 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.