公开(公告)号：US20230135902A1

公开(公告)日：2023-05-04

申请号：US18091303

申请日：2022-12-29

Applicant: Kioxia Corporation

Inventor： Xu LI

IPC: G11C16/04 ,  H10B43/27 ,  G11C16/26

Abstract: A semiconductor memory device includes a first memory string including a first select transistor, a first memory cell, a first select element, a second memory cell, and a second select element in series, a second memory string including a second select transistor, a third memory cell, a third select element, a fourth memory cell, and a fourth select element in series, and a control circuit. The control circuit is configured to set the second select transistor to an on state, and to set the third select element and the fourth select element to an off state, when reading data of the first memory cell.

公开(公告)号：US20230093270A1

公开(公告)日：2023-03-23

申请号：US17654292

申请日：2022-03-10

Applicant: Kioxia Corporation

Inventor： Xu LI

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor storage device of an embodiment includes a plurality of blocks, a voltage supply circuit configured to generate read voltage Vr to be supplied to signal lines, a block decoder capable of setting, for each of the selected blocks, whether the read voltage Vr is applied to word lines, and a sequencer configured to perform operation that reads data. The voltage supply circuit generates power voltage VRD and power voltage VBB that is negative voltage and supplies these voltages to the block decoder. During the reading operation, a value of the power voltage VRD is changed between voltage Vhr and voltage Vlr and a value of the power voltage VBB is changed between voltage Vhb and voltage Vlb. The voltage Vhr is larger than zero volt, and the voltage Vlb is lower than zero volt.

公开(公告)号：US20220093178A1

公开(公告)日：2022-03-24

申请号：US17541103

申请日：2021-12-02

Applicant: KIOXIA CORPORATION

Inventor： Xu LI

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/30 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

Abstract: A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.

公开(公告)号：US20250095741A1

公开(公告)日：2025-03-20

申请号：US18964133

申请日：2024-11-29

Applicant: Kioxia Corporation

Inventor： Xu LI

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  H10B69/00

Abstract: A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.

公开(公告)号：US20220301599A1

公开(公告)日：2022-09-22

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Xu LI ,  Masayuki MIURA ,  Takayuki MIYAZAKI ,  Toshio FUJISAWA ,  Hiroto NAKAI ,  Hideko MUKAIDA ,  Mie MATSUO

IPC: G11C5/14 ,  H01L27/11556 ,  H01L27/11582 ,  H02M3/158 ,  G11C16/30

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US20220020432A1

公开(公告)日：2022-01-20

申请号：US17200701

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Xu LI

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor, a second memory cell transistor, and a first select element that connects the first memory cell transistor and the second memory cell transistor in series, a second memory string including a third memory cell transistor, a fourth memory cell transistor, and a second select element that connects the third memory cell transistor and the fourth memory cell transistor in series, and a control circuit. The control circuit is configured to set the second select element to an off state while setting the first select element to an on state when reading data of the first memory string.

公开(公告)号：US20210295916A1

公开(公告)日：2021-09-23

申请号：US17010564

申请日：2020-09-02

Applicant: KIOXIA CORPORATION

Inventor： Xu LI

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

Abstract: A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.