公开(公告)号：US12001339B2

公开(公告)日：2024-06-04

申请号：US17940138

申请日：2022-09-08

Applicant: Kioxia Corporation

Inventor： Daisuke Yashima ,  Sho Kodama ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Youhei Fukazawa ,  Zheye Wang ,  Kohei Oikawa ,  Takashi Miura

IPC: G06F12/00 ,  G06F12/0875 ,  H03M7/30

CPC classification number: G06F12/0875 ,  G06F2212/1044 ,  G06F2212/401

Abstract: According to one embodiment, a dictionary buffer stores dictionary data including a first substring and data before the first substring. A substring generator generates, from second input data, second substrings. A transformer transforms each of the second substrings into a hash value. A read processor reads the dictionary data, using a hash value transformed from a third substring among the second substrings. An acquisition unit compares a data string including the third substring and data before the third substring with the read dictionary data, and acquire first and second match lengths of the third and fourth substrings. A coded data generator generates coded data based on the acquired first and second match lengths.

公开(公告)号：US11868615B2

公开(公告)日：2024-01-09

申请号：US17471107

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Youhei Fukazawa ,  Kohei Oikawa ,  Sho Kodama ,  Keiri Nakanishi ,  Takashi Miura ,  Daisuke Yashima ,  Masato Sumiyoshi ,  Zheye Wang

IPC: G06F3/06 ,  H03M7/30

CPC classification number: G06F3/0608 ,  G06F3/0638 ,  G06F3/0646 ,  G06F3/0683 ,  H03M7/3084

Abstract: According to one embodiment, a compression device includes a first storage unit, a second storage unit, a calculation unit, and a comparison unit. The first storage unit stores addresses associated with hash values, respectively. The second storage unit includes storage areas specified by the addresses, respectively. The calculation unit determines a hash function to be used for first data in accordance with at least a part of the first data, and calculates a hash value using the hash function and at least a part of second data included in the first data. The comparison unit acquires third data from a storage area in the second storage unit specified by a first address, and compares the second data with the third data. The first address is stored in the first storage unit and is associated with the hash value.

公开(公告)号：US12108064B2

公开(公告)日：2024-10-01

申请号：US18479521

申请日：2023-10-02

Applicant: KIOXIA CORPORATION

Inventor： Daisuke Yashima ,  Masato Sumiyoshi ,  Keiri Nakanishi ,  Takashi Miura ,  Kohei Oikawa ,  Sho Kodama ,  Youhei Fukazawa ,  Zheye Wang

IPC: H04N19/423 ,  H04N19/13 ,  H04N19/146 ,  H04N19/184

CPC classification number: H04N19/423 ,  H04N19/13 ,  H04N19/146 ,  H04N19/184

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US11726711B2

公开(公告)日：2023-08-15

申请号：US17184218

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Zheye Wang ,  Akiyuki Kaneko

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received.

公开(公告)号：US11818376B2

公开(公告)日：2023-11-14

申请号：US17868597

申请日：2022-07-19

Applicant: Kioxia Corporation

Inventor： Daisuke Yashima ,  Masato Sumiyoshi ,  Keiri Nakanishi ,  Takashi Miura ,  Kohei Oikawa ,  Sho Kodama ,  Youhei Fukazawa ,  Zheye Wang

IPC: H04N19/423 ,  H04N19/146 ,  H04N19/13 ,  H04N19/184

CPC classification number: H04N19/423 ,  H04N19/13 ,  H04N19/146 ,  H04N19/184

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US11588498B2

公开(公告)日：2023-02-21

申请号：US17472431

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Daisuke Yashima ,  Kohei Oikawa ,  Sho Kodama ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Youhei Fukazawa ,  Zheye Wang ,  Takashi Miura

IPC: H03M7/30 ,  G06F3/06 ,  G11C16/04

Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

公开(公告)号：US20210294525A1

公开(公告)日：2021-09-23

申请号：US16942112

申请日：2020-07-29

Applicant: Kioxia Corporation

Inventor： Masato Sumiyoshi ,  Keiri Nakanishi ,  Takashi Miura ,  Kohei Oikawa ,  Daisuke Yashima ,  Sho Kodama ,  Youhei Fukazawa ,  Zheye Wang

IPC: G06F3/06 ,  H03M7/30

Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by refferring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.

公开(公告)号：US11899934B2

公开(公告)日：2024-02-13

申请号：US17686246

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Youhei Fukazawa ,  Sho Kodama ,  Keiri Nakanishi ,  Kohei Oikawa ,  Takashi Miura ,  Daisuke Yashima ,  Masato Sumiyoshi ,  Zheye Wang

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.

公开(公告)号：US11824566B2

公开(公告)日：2023-11-21

申请号：US17696756

申请日：2022-03-16

Applicant: Kioxia Corporation

Inventor： Zheye Wang ,  Keiri Nakanishi ,  Kohei Oikawa ,  Masato Sumiyoshi ,  Sho Kodama ,  Youhei Fukazawa ,  Daisuke Yashima ,  Takashi Miura

IPC: H03M7/40 ,  H03M7/42 ,  H03M7/30

CPC classification number: H03M7/4093 ,  H03M7/42 ,  H03M7/6005

Abstract: According to one embodiment, a data decompression device includes: a detection circuit configured to detect a boundary between a header and a payload in a compressed stream, based on boundary information in the header; a separation circuit configured to separate the header and the payload; a first decompression circuit configured to decompress a compressed coding table in the header; and a second decompression circuit configured to decompress the payload, based on an output of the first decompression circuit.

公开(公告)号：US11651833B2

公开(公告)日：2023-05-16

申请号：US17680128

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Kohei Oikawa ,  Keiri Nakanishi ,  Sho Kodama ,  Masato Sumiyoshi ,  Daisuke Yashima ,  Youhei Fukazawa ,  Zheye Wang ,  Takashi Miura

IPC: G11C29/42 ,  H03M13/00 ,  H03M13/09

CPC classification number: G11C29/42 ,  H03M13/091 ,  H03M13/611

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.