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    High pressure reoxidation anneal of silicon nitride for reduced thermal budget silicon processing
    1.
    发明授权
    High pressure reoxidation anneal of silicon nitride for reduced thermal budget silicon processing 失效
    氮化硅的高压再氧化退火，用于减少热预算硅处理

    公开(公告)号：US5624865A

    公开(公告)日：1997-04-29

    申请号：US542979

    申请日：1995-10-13

    申请人： Klaus F. Schuegraf ,  Randhir P. S. Thakur ,  Pierre C. Fazan

    发明人： Klaus F. Schuegraf ,  Randhir P. S. Thakur ,  Pierre C. Fazan

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/1085 ,  H01L28/40

    摘要： A semiconductor integrated circuit fabrication method is provided for forming a capacitor on a semiconductor integrated circuit substrate. A lower capacitor electrode is formed over the semiconductor integrated circuit substrate and a capacitor dielectric is formed over the lower capacitor electrode. The capacitor dielectric is preferably formed of silicon nitride. A reoxidation anneal of the capacitor dielectric is performed at a pressure greater than one atmosphere in order to form an oxide layer over the capacitor dielectric. An upper capacitor electrode is disposed over the oxide layer to form a capacitor. The capacitor is formed as part of a dynamic random access memory cell. A transistor is formed upon the semiconductor integrated circuit substrate and the lower capacitor electrode is formed in electrical contact with a diffusion region of the transistor. The capacitor is formed within an opening in molding material that is deposited over the surface of the semiconductor integrated circuit substrate. The reoxidization anneal of the capacitor dielectric is performed at a temperature in the range of 600.degree. C. to 800.degree. C. at pressures ranging up to twenty-five atmospheres. This forms an oxide layer having a thickness between five angstroms and fifteen angstroms in a period of time short enough to prevent excessive out diffusion of dopants from the diffusion regions of the transistor.

    摘要翻译： 提供半导体集成电路制造方法，用于在半导体集成电路基板上形成电容器。 在半导体集成电路基板上形成下电容电极，在下电容器电极上形成电容电介质。 电容器电介质优选由氮化硅形成。 电容器电介质的再氧化退火在大于1个大气压的压力下进行，以便在电容器电介质上形成氧化物层。 上电容器电极设置在氧化物层上以形成电容器。 电容器形成为动态随机存取存储器单元的一部分。 晶体管形成在半导体集成电路基板上，而下电容器电极形成为与晶体管的扩散区域电接触。 电容器形成在沉积在半导体集成电路基板的表面上的成型材料的开口内。 电容器电介质的再氧化退火在高达二十五个大气压的压力下在600℃至800℃的温度范围内进行。 这形成了在足够短的时间内形成厚度在五埃至十五埃之间的氧化物层，以防止掺杂剂从晶体管的扩散区过度扩散。

    Methods of forming capacitors and related integrated circuitry
    3.
    发明授权
    Methods of forming capacitors and related integrated circuitry 失效
    形成电容器和相关集成电路的方法

    公开(公告)号：US06222222B1

    公开(公告)日：2001-04-24

    申请号：US09156207

    申请日：1998-09-17

    申请人： Scott J. DeBoer ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    发明人： Scott J. DeBoer ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L27/10811 ,  H01L28/91

    摘要： Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to be rougher than at least some of the internal container surface. A capacitor dielectric layer and an outer capacitor plate layer are formed over at least portions of the internal and the external surfaces of the capacitor container. In another implementation, a layer comprising roughened polysilicon is formed over at least some of the external container surface but not over any of the internal container surface. In a preferred aspect, the roughened external surface or roughened polysilicon comprises hemispherical grain polysilicon.

    摘要翻译： 描述了电容器结构及其形成方法。 在一个实施方案中，电容器容器形成在衬底上并且包括内表面和外表面。 至少一些外表面被提供为比内部容器表面中的至少一些更粗糙。 在电容器容器的内表面和外表面的至少一部分上形成电容器介电层和外电容器板层。 在另一个实施方案中，包含粗糙多晶硅的层形成在至少一些外部容器表面上，但不在任何内部容器表面上。 在优选的方面，粗糙化的外表面或粗糙多晶硅包括半球形晶粒多晶硅。

    Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon
    7.
    发明授权
    Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon 失效
    提供半导体晶粒多晶硅的导电掺杂层的半导体加工方法

    公开(公告)号：US5639685A

    公开(公告)日：1997-06-17

    申请号：US539851

    申请日：1995-10-06

    申请人： John K. Zahurak ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    发明人： John K. Zahurak ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    IPC分类号： H01L21/02 ,  H01L21/70

    CPC分类号： H01L28/84 ,  Y10S148/138

    摘要： A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350.degree. C. to about 600.degree. C. and at an annealing pressure of from about 10.sup.-4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.

    摘要翻译： 在衬底上提供半球形晶粒多晶硅的导电掺杂层的半导体处理方法包括：a）在衬底上提供厚度大于约200埃的导电掺杂硅层; b）在掺杂硅层上沉积未掺杂的非多晶硅层至厚度为100埃至约400埃; c）将衬底与掺杂的硅和未掺杂的非多晶硅层定位在化学气相沉积反应器内; d）与其中的基底，将化学气相沉积反应器内的压力降低到等于或低于约200mTorr的第一压力; e）与其中的基板，从第一压力升高化学气相沉积反应器内的压力并用净化气体冲洗反应器; f）其中衬底在其中停止清洗气体的流动并且将化学气相沉积反应器内的压力降低至等于或低于约200mTorr的第二压力; 以及g）在约350℃至约600℃的退火温度和约10℃的退火温度下，在导电性增强杂质气体存在下退火具有沉积的非多晶硅层的衬底， 4乇至约80乇原位扩散导电性增强杂质进入非多晶硅层，并将非多晶硅层转变为导电掺杂半球形晶粒多晶硅层。

    Methods of forming capacitors and related integrated circuitry
    8.
    发明授权
    Methods of forming capacitors and related integrated circuitry 失效
    形成电容器和相关集成电路的方法

    公开(公告)号：US06404005B1

    公开(公告)日：2002-06-11

    申请号：US09823133

    申请日：2001-03-29

    申请人： Scott J. DeBoer ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    发明人： Scott J. DeBoer ,  Klaus F. Schuegraf ,  Randhir P. S. Thakur

    IPC分类号： H01L21108

    CPC分类号： H01L28/84 ,  H01L27/10811 ,  H01L28/91 ,  H01L28/92

    摘要： Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to be rougher than at least some of the internal container surface. A capacitor dielectric layer and an outer capacitor plate layer are formed over at least portions of the internal and the external surfaces of the capacitor container. In another implementation, a layer comprising roughened polysilicon is formed over at least some of the external container surface but not over any of the internal container surface. In a preferred aspect, the roughened external surface or roughened polysilicon comprises hemispherical grain polysilicon.

    摘要翻译： 描述了电容器结构及其形成方法。 在一个实施方案中，电容器容器形成在衬底上并且包括内表面和外表面。 至少一些外表面被提供为比内部容器表面中的至少一些更粗糙。 在电容器容器的内表面和外表面的至少一部分上形成电容器介电层和外电容器板层。 在另一个实施方案中，包含粗糙多晶硅的层形成在至少一些外部容器表面上，但不在任何内部容器表面上。 在优选的方面，粗糙化的外表面或粗糙多晶硅包括半球形晶粒多晶硅。

    DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
    10.
    发明授权
    DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films 失效
    由硅锗制成的DRAM电容器和电极限制导电介电膜

    公开(公告)号：US6150208A

    公开(公告)日：2000-11-21

    申请号：US76333

    申请日：1998-05-11

    申请人： Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

    发明人： Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/40 ,  H01L27/10852

    摘要： An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between said first and second plates, with the dielectric layer being dominated by electrode-limited conduction, which includes tantalum pentoxide and silicon nitride, or a combination of the two. In a preferred implementation, one of the two capacitor plates is formed from a silicon-germanium layer, the second plate is formed from a metal and the dielectric layer is formed from tantalum pentoxide.

    摘要翻译： 本发明的示例性实施例包括一种用于具有第一板的动态随机存取存储单元的电容器; 第二盘 以及插入在所述第一和第二板之间的电介质层，其中所述电介质层由电极限制导电支配，其包括五氧化二钽和氮化硅，或两者的组合。 在优选的实施方式中，两个电容器板之一由硅 - 锗层形成，第二板由金属形成，并且介电层由五氧化二钽形成。