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1.发明授权
公开(公告)号：US4531089A
公开(公告)日：1985-07-23
申请号：US348013
申请日：1982-02-11
申请人： Kohei Ishizuka , Yasuhiro Kita , Narimichi Maeda , Masahiro Koya , Kazuhiko Takaoka , Yoshiro Kokuryo
发明人： Kohei Ishizuka , Yasuhiro Kita , Narimichi Maeda , Masahiro Koya , Kazuhiko Takaoka , Yoshiro Kokuryo
IPC分类号： G01R21/133 , H03G3/20 , G01R17/06 , G01R1/30 , G01R21/00
CPC分类号： H03G1/0088 , G01R21/133 , H03G3/30 , H03G3/3052
摘要： In a gain control circuit, an electric power calculating circuit is connected to a variable gain amplifier and a gain setting circuit for generating a gain control signal applied to the variable gain amplifier to control the gain thereof.
摘要翻译： 在增益控制电路中，电力计算电路连接到可变增益放大器和增益设置电路，用于产生施加到可变增益放大器以控制其增益的增益控制信号。
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公开(公告)号：US4477913A
公开(公告)日：1984-10-16
申请号：US368664
申请日：1982-04-15
申请人： Masahiro Koya , Narimichi Maeda , Kohei Ishizuka , Kazuhiko Takaoka , Yoshiro Kokuryo , Yasuhiro Kita
发明人： Masahiro Koya , Narimichi Maeda , Kohei Ishizuka , Kazuhiko Takaoka , Yoshiro Kokuryo , Yasuhiro Kita
CPC分类号： H04L27/01
摘要： An equalizer apparatus suitable for use in a MODEM for receiving a signal having passed through a number of carrier-band lines is disclosed in which the number of carrier-band lines is detected from a training signal, and electrical connection of a fixed equalizer to a variable equalizer is controlled on the basis of the number of carrier-band lines, in order to form a precise, simple automatic equalizer apparatus.
摘要翻译： 公开了一种适用于MODEM中用于接收已经通过多个载波频带的信号的均衡器装置，其中从训练信号检测载波带数的数目，并将固定均衡器与 可变均衡器基于载波频带数量进行控制，以便形成精确，简单的自动均衡器装置。
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公开(公告)号：US4004253A
公开(公告)日：1977-01-18
申请号：US587894
申请日：1975-06-18
摘要： An inductorless variable equalizer comprises input and output terminals. A first transmission network is situated in the forward path between the input and output terminals and has a variable transfer coefficient; second and third transmission networks are situated in the feedback and feedforward paths, respectively, between the input and output terminals. Each of these networks has a fixed transfer coefficient and the transfer coefficients of the feedback and feedforward networks having polarities opposite each other.
摘要翻译： 无电感可变均衡器包括输入和输出端子。 第一传输网络位于输入和输出端之间的前向路径中，具有可变传输系数; 第二和第三传输网络分别位于输入和输出端之间的反馈和前馈路径中。 这些网络中的每一个具有固定的传输系数和具有彼此相反的极性的反馈和前馈网络的传输系数。
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公开(公告)号：US4292596A
公开(公告)日：1981-09-29
申请号：US66239
申请日：1979-08-13
申请人： Kohei Ishizuka , Yasuhiro Kita , Narimichi Maeda
发明人： Kohei Ishizuka , Yasuhiro Kita , Narimichi Maeda
摘要： A circuit for varying the gain of an amplifier circuit linearly in decibel by the use of a digital code signal varying linearly, wherein a resistance network to be connected between an amplifier having a fixed gain and an input or output portion for the amplification is connected and the gain of the amplifier as well as the values of resistance elements constituting the resistance network is set so that the transfer function of the amplifier circuit may become: ##EQU1## .
摘要翻译： 一种用于通过使用线性变化的数字码信号以分贝线性地改变放大器电路的增益的电路，其中连接在具有固定增益的放大器和用于放大的输入或输出部分之间的电阻网络被连接， 设置放大器的增益以及构成电阻网络的电阻元件的值，使得放大器电路的传递函数可以变为：
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公开(公告)号：US4441192A
公开(公告)日：1984-04-03
申请号：US294229
申请日：1981-08-19
申请人： Yasuhiro Kita , Nobuo Tsukamoto , Masahiro Koya , Narimichi Maeda
发明人： Yasuhiro Kita , Nobuo Tsukamoto , Masahiro Koya , Narimichi Maeda
CPC分类号： H04L25/03133 , H04B3/142
摘要： A signal processing system detects the transmission characteristics of a channel thereby to compensate the output waveform of the channel into the most-optimum state. The impulse response of the channel is detected by transmitting a code having a keen autocorrelation from the transmission end and by determining the correlation between the received signal of the code transmitted and the same code of the aforementioned code at a reception end.
摘要翻译： 信号处理系统检测通道的传输特性，从而将通道的输出波形补偿到最佳状态。 通过从发送端发送具有敏锐自相关性的代码，并且通过确定发送的代码的接收信号和接收端的上述代码的相同代码之间的相关性来检测信道的脉冲响应。
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6.发明授权
公开(公告)号：US4620292A
公开(公告)日：1986-10-28
申请号：US700908
申请日：1985-02-12
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.
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7.发明授权Digital processor with floating point multiplier and adder suitable for digital signal processing 失效具有浮点乘法器和加法器的数字处理器适用于数字信号处理
公开(公告)号：US4511990A
公开(公告)日：1985-04-16
申请号：US311680
申请日：1981-10-15
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.
摘要翻译： 具有宽动态范围并且可以通过使用单个浮点运算电路处理固定点表示中的数据和浮点表示中的数据的信号处理器能够处理诸如语音信号之类的数字信号 高速和实时。 此外，该信号处理器能够以固定点表示的数据格式的外部电路执行数据输入/输出操作，并且以浮点表示格式执行内部操作。 此外，可以根据程序指令在内部将操作结果从固定点表示转换为浮点表示，反之亦然。
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公开(公告)号：US4592006A
公开(公告)日：1986-05-27
申请号：US700907
申请日：1985-02-12
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.
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9.发明授权
公开(公告)号：US4534010A
公开(公告)日：1985-08-06
申请号：US313507
申请日：1981-10-21
CPC分类号： G06F7/4876 , G06F7/5443 , G06F7/49921
摘要： According to the present invention, a normalized floating point type multiplier circuit including a multiplier for mantissa's multiplication and an adder for exponent's addition is equipped with both a detector circuit for detecting over- and under-flows and a compensation circuit for compensating the output of said multiplier without any programming, when the over- and under-flows are detected, so that the multiplying speed can be improved.
摘要翻译： 根据本发明，包括用于尾数乘法的乘法器和用于指数相加的加法器的归一化浮点型乘法器电路配备有用于检测过流和欠流的检测器电路和补偿电路，用于补偿所述 当没有任何编程时，当检测到过流和欠流时，可以提高乘法速度。
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公开(公告)号：US4337518A
公开(公告)日：1982-06-29
申请号：US172947
申请日：1980-07-28
CPC分类号： H03H17/0461
摘要： A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal x.sub.n inputted at a predetermined sampling period and an output signal y.sub.n-k fed back to the input of the calculation circuit in accordance with the input signal x.sub.n after being subjected to a delay of k sampling periods by a.sub.k and b.sub.k coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data y.sub.n of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data y.sub.n as an output signal corresponding to the input signal x.sub.n.The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data y.sub.n so that the b.sub.k coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data y.sub.n, thereby to produce an output signal with reduced round off noise.
摘要翻译： 一种包括计算电路的递归型数字滤波器。 计算电路被配置为将包括在预定采样周期输入的至少m位信号xn和输入信号yn-k的输入信号乘以运算电路的输入，根据输入信号xn 分别对应于滤波器特性的ak和bk系数的k个采样周期的延迟，然后将乘积相加以产生满足
的（m + 1）比特的数据yn，并且串行地传送上m- 数据yn的位数据作为与输入信号xn对应的输出信号。 滤波器还包括延迟电路，用于将包括数据yn的第（m + 1）位的舍入数据的一部分反馈给计算电路的输入，使得bk系数乘以 第（m + 1）位和乘积被加到数据yn，从而产生具有减小的舍入噪声的输出信号。
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