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1.发明授权Desk-top information processing apparatus having a height greater than its front surface width, a first leg with a cut-out for cooling air, and a second leg with non-aligned ends 失效具有高于其前表面宽度的高度的桌面信息处理设备，具有用于冷却空气的切口的第一腿部以及具有非对齐端部的第二腿部
公开(公告)号：US5457602A
公开(公告)日：1995-10-10
申请号：US617880
申请日：1990-11-26
申请人： Koichi Kimura , Takashi Maruyama , Nobukazu Kondo , Hiroaki Aotsu , Michikazu Isono , Shoji Matsui , Toshiyuki Edakawa , Sadao Nakatsuka , Toshio Shibata , Mitsuji Suzuki , Yoshio Kakihi , Chihiro Tsuchiya , Tetuya Fukunaga , Takao Ohsawa , Noriyoshi Ogura
发明人： Koichi Kimura , Takashi Maruyama , Nobukazu Kondo , Hiroaki Aotsu , Michikazu Isono , Shoji Matsui , Toshiyuki Edakawa , Sadao Nakatsuka , Toshio Shibata , Mitsuji Suzuki , Yoshio Kakihi , Chihiro Tsuchiya , Tetuya Fukunaga , Takao Ohsawa , Noriyoshi Ogura
摘要： A data processing apparatus comprising a disk unit, a power supply unit, at least one printed circuit board, a heat-exhaust fan, and a box accommodating the disk unit, the power supply unit, the printed circuit board, the heat-exhaust fan. Both the depth and height of the box are larger than the width and has first and second side surfaces defined by the depth and height, bottom and top surfaces defined by the depth and width, and front and rear surfaces defined the height and width. The disk unit and the power supply unit are disposed adjacent to the first side surface. The printed circuit board is disposed adjacent to the second side surface. The disk unit is disposed on the front surface, and the power supply unit is disposed on the rear surface. The apparatus is supported by a first leg and a second leg. Cooling air is exhausted through the first leg which includes a cut-out which communicates with a hollow portion. The second leg includes two non-aligned ends which extend beyond the sides of the apparatus and allow two of the apparatuses to be placed side by side.
摘要翻译： 一种数据处理装置，包括盘单元，电源单元，至少一个印刷电路板，散热风扇和容纳盘单元的盒，电源单元，印刷电路板，排热风扇 。 盒子的深度和高度都大于宽度，并且具有由深度和宽度限定的深度和高度，底部和顶部表面以及前后表面限定高度和宽度的第一和第二侧面。 盘单元和电源单元设置成与第一侧表面相邻。 印刷电路板与第二侧面相邻配置。 盘单元设置在前表面上，并且电源单元设置在后表面上。 该装置由第一腿和第二腿支撑。 冷却空气通过第一腿排出，该第一腿包括与中空部分连通的切口。 第二腿包括延伸超过设备侧面的两个不对齐的端部，并且允许两个装置并排放置。
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2.发明授权Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display 失效图形系统包括用于在图形显示器上显示像素数据的多个单芯片半导体集成电路器件
公开(公告)号：US5838337A
公开(公告)日：1998-11-17
申请号：US294406
申请日：1994-08-23
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal. Further the logic circuit of the one-chip semiconductor integrated circuit device outputs pixel data based on the logic operation carried out by the logic circuit so as to display the pixel data from the logic circuit on one of the display portions of the graphic display area of the display device.
摘要翻译： 一种包括具有包括多个显示部分和多个单芯片半导体集成电路装置的图形显示区域的显示装置的图形系统。 每个单芯片半导体集成电路包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及用于对从存储器读出的一个像素数据的单元执行逻辑运算的逻辑电路 基于提供给单芯片半导体集成电路器件的功能信号。 功能信号表示从存储器读出的一个像素数据的单位与由逻辑电路输出的像素数据之间的关系。 本发明还包括用于将功能信号提供给单芯片半导体集成电路器件的外部器件。 多个单芯片半导体集成电路装置的逻辑电路各自根据功能信号执行相同的逻辑运算。 此外，单芯片半导体集成电路器件的逻辑电路基于由逻辑电路执行的逻辑运算输出像素数据，以便在逻辑电路的图形显示区域的显示部分之一上显示来自逻辑电路的像素数据 显示设备。
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公开(公告)号：US5592649A
公开(公告)日：1997-01-07
申请号：US279843
申请日：1994-07-26
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. utilizing presetting in a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.
摘要翻译： 包括可以任意执行数据读取，写入和存储操作的存储器元件的存储器电路，存储元件具有二进制/算术运算功能。 利用在读/写/写模式下的预置在存储器周期中执行，并且在来自存储器元件的数据和来自外部设备的数据存在的间隔中，在外部数据和存储元件中的数据之间执行操作 并且在写入周期期间存储操作结果，从而实现更高速的操作。
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公开(公告)号：US5175816A
公开(公告)日：1992-12-29
申请号：US641064
申请日：1991-01-14
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
IPC分类号： G06F9/308
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes, a second address operation unit for updating the address of data in units of a bit or multiple bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或多字节为单位更新数据单元的地址，以单字节或多字节为单位执行操作;第二地址操作单元，用于以 位或多位，地址控制装置，用于响应于由第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址;以及装置，用于获取用于操作的字节宽数据， 第一地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。
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公开(公告)号：US4849907A
公开(公告)日：1989-07-18
申请号：US848459
申请日：1986-04-07
CPC分类号： G09G5/393 , G06T11/203
摘要： In a draw processing apparatus for drawing a character, pattern or image; a segment element of a horizontal or vertical continuous run length, a coordinate of a start point of the segment and a direction coefficient of the segment are calculated, a boundary coordinate of a draw area in which a data is to be drawn is calculated in accordance with a position and a size of the draw area, a valid portion and an invalid portion of the segment are calculated for each segment element for the result first calculation result in accordance with the second calculation result, and the valid segment portion is drawn in accordance with the first calculation result.
摘要翻译： 在用于绘制字符，图案或图像的绘制处理装置中; 计算水平或垂直连续行程长度的段元素，段的开始点的坐标和段的方向系数，根据其中绘制数据的绘制区域的边界坐标 根据第二计算结果，针对结果第一计算结果针对每个段元素计算绘制区域的位置和大小，对于段的有效部分和无效部分，并根据第二计算结果绘制有效段部分 具有第一个计算结果。
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6.发明授权One chip semiconductor integrated circuit device for displaying pixel data on a graphic display 失效一种用于在图形显示器上显示像素数据的芯片半导体集成电路器件
公开(公告)号：US5767864A
公开(公告)日：1998-06-16
申请号：US294405
申请日：1994-08-23
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.
摘要翻译： 一种用于在显示装置的图形显示区域上显示像素数据的装置。 图形显示区域包括多个显示部分。 本发明包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及逻辑电路，用于对从存储器读出的一个像素数据的单位的组合进行逻辑运算 并提供给设备的外部数据。 逻辑电路基于逻辑运算输出像素数据，以便在显示装置的图形显示区域的一个显示部分上显示像素数据。
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公开(公告)号：US5617360A
公开(公告)日：1997-04-01
申请号：US588232
申请日：1996-01-18
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
摘要翻译： 形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器 用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元 以及从第二输入提供的第二数据。 操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。 从存储位置的选定部分读出第二数据。 对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。 在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。
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公开(公告)号：USRE33922E
公开(公告)日：1992-05-12
申请号：US542028
申请日：1990-06-21
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyouda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyouda
CPC分类号： G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.
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公开(公告)号：US5113487A
公开(公告)日：1992-05-12
申请号：US314238
申请日：1989-02-22
IPC分类号： G09G5/393
CPC分类号： G09G5/393 , G09G2340/10
摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in a read-modify-write mode can be used commonly.
摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写入控制数据中的一个的选择器具有选择控制信号，使得可以通常使用以读 - 修改 - 写入模式操作的帧缓冲存储器。
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公开(公告)号：US4868781A
公开(公告)日：1989-09-19
申请号：US240380
申请日：1988-08-29
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.
摘要翻译： 一种存储器电路，包括可任意执行数据读取，写入和存储操作的存储器元件，存储器元件具有二进制/算术运算功能。 在存储器周期内要执行的读取/修改/写入模式以及来自存储器元件和来自外部设备的数据的数据存在的间隔中，在外部数据和存储器元件中的数据之间执行操作，并且结果 在写入周期期间存储这种操作，从而实现更高速的操作。
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