公开(公告)号：US07109128B2

公开(公告)日：2006-09-19

申请号：US10866763

申请日：2004-06-15

申请人： Koichi Sugiyama ,  Yoshihiro Takao ,  Shinji Sugatani ,  Daisuke Matsunaga ,  Takayuki Wada ,  Tohru Fujita ,  Hikaru Kokura

发明人： Koichi Sugiyama ,  Yoshihiro Takao ,  Shinji Sugatani ,  Daisuke Matsunaga ,  Takayuki Wada ,  Tohru Fujita ,  Hikaru Kokura

IPC分类号： H01L21/302

CPC分类号： H01L29/665 ,  H01L21/26586 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/1083 ,  H01L29/6656 ,  Y10S257/90

摘要： There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

公开(公告)号：US06800909B2

公开(公告)日：2004-10-05

申请号：US10261695

申请日：2002-10-02

申请人： Koichi Sugiyama ,  Yoshihiro Takao ,  Shinji Sugatani ,  Daisuke Matsunaga ,  Takayuki Wada ,  Tohru Fujita ,  Hikaru Kokura

发明人： Koichi Sugiyama ,  Yoshihiro Takao ,  Shinji Sugatani ,  Daisuke Matsunaga ,  Takayuki Wada ,  Tohru Fujita ,  Hikaru Kokura

IPC分类号： H01L2120

CPC分类号： H01L29/665 ,  H01L21/26586 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/1083 ,  H01L29/6656 ,  Y10S257/90

摘要： There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

摘要翻译： 提供了通过栅极绝缘膜形成在一种导电类型的半导体衬底上的栅电极，形成在栅电极的两个侧表面上并且在栅电极和半导体的上表面之间具有间隔的离子注入控制膜 衬底，相反导电类型的第一和第二杂质扩散区形成在栅电极两侧的半导体衬底中并且用作源极/漏极，形成在第一和第二杂质扩散之间的栅电极下面的一种导电类型的沟道区 具有相反导电类型的区域和一个导电类型的袋区域连接到在栅极电极下方的半导体衬底中的相反导电类型的杂质扩散区域的端部，并且具有比沟道区域高的一种导电类型的杂质浓度。

公开(公告)号：US20060022242A1

公开(公告)日：2006-02-02

申请号：US11017828

申请日：2004-12-22

申请人： Shinji Sugatani ,  Koichi Hashimoto ,  Yoshihiro Takao

发明人： Shinji Sugatani ,  Koichi Hashimoto ,  Yoshihiro Takao

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.

摘要翻译： 半导体器件包括具有沟槽16a和形成在其中的沟槽16b的半导体衬底10; 掩埋在沟槽16a中的器件隔离膜32a，其包括含有氮化硅膜20和氧化硅类绝缘材料的绝缘膜28的衬垫膜; 掩埋在沟槽16b的底部的器件隔离膜32b; 以及形成在第二沟槽16b的上部的侧壁上并且包括作为第一电极的杂质扩散区域40，氧化硅类绝缘膜的电容器电介质膜43和第二电极46的电容器。

公开(公告)号：US07414278B2

公开(公告)日：2008-08-19

申请号：US11017828

申请日：2004-12-22

申请人： Shinji Sugatani ,  Koichi Hashimoto ,  Yoshihiro Takao

发明人： Shinji Sugatani ,  Koichi Hashimoto ,  Yoshihiro Takao

IPC分类号： H01L27/108

CPC分类号： H01L27/1087 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.

摘要翻译： 半导体器件包括具有沟槽16a和形成在其中的沟槽16b的半导体衬底10; 掩埋在沟槽16a中的器件隔离膜32a，其包括含有氮化硅膜20和氧化硅类绝缘材料的绝缘膜28的衬垫膜; 掩埋在沟槽16b的底部的器件隔离膜32b; 以及形成在第二沟槽16b的上部的侧壁上并且包括作为第一电极的杂质扩散区域40，氧化硅类绝缘膜的电容器电介质膜43和第二电极46的电容器。

公开(公告)号：US20110006379A1

公开(公告)日：2011-01-13

申请号：US12824591

申请日：2010-06-28

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

摘要： A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

摘要翻译： 半导体器件包括其中限定了存储单元的有源区的硅衬底，形成在器件隔离绝缘膜上以在第一方向上延伸的栅电极，形成在硅衬底和栅电极上的第一绝缘膜， 所述第一插塞形成为穿透所述第一绝缘膜，与所述栅极电极和所述第一有源区域重叠，并且在垂直于所述第一方向的第二方向上延伸，穿过所述第二有源区域上方的所述第一绝缘膜的第二插塞， 形成在第一绝缘膜上的第二绝缘膜和埋在第二绝缘膜中的互连，并且形成为沿着第二方向从第一插塞的侧表面退回并且仅覆盖第一插头的上表面的一部分。

公开(公告)号：US07470973B2

公开(公告)日：2008-12-30

申请号：US11411888

申请日：2006-04-27

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7843

摘要： In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.

摘要翻译： 在p沟道MOS晶体管和n沟道MOS晶体管的每一个中，沟道方向设定在<100>方向，并且在STI器件隔离结构中形成累积其中的拉伸应力的第一应力腐蚀膜。 此外，在硅衬底上形成积累有拉伸应力的第二应力源膜，以覆盖器件隔离结构。

公开(公告)号：US06251721B1

公开(公告)日：2001-06-26

申请号：US09545598

申请日：2000-04-07

申请人： Kenichi Kanazawa ,  Koichi Hashimoto ,  Yoshihiro Takao ,  Masaki Katsube

发明人： Kenichi Kanazawa ,  Koichi Hashimoto ,  Yoshihiro Takao ,  Masaki Katsube

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888

摘要： After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.

摘要翻译： 在SAC膜形成为不填充存储单元区域中的栅电极之间的空间的厚度之后，形成氧化硅膜以使其填充空间。 在外围电路区域的仅栅电极的侧面上形成由氧化硅膜构成的侧壁，在露出的基板表面上形成金属硅化物。 在整个表面上形成BLC膜。 使用SAC膜和BLC膜自对准地形成接触孔。 在这种方法中，外围电路区域中的晶体管的源极/漏极的硅化和诸如BLC或SAC之类的自对准技术可以被同时使用，从而能够增加半导体器件的集成度和性能的提高 在逻辑电路中的晶体管上具有金属硅化物。

公开(公告)号：US08569126B2

公开(公告)日：2013-10-29

申请号：US13584253

申请日：2012-08-13

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

摘要： A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

摘要翻译： 半导体器件包括其中限定了存储单元的有源区的硅衬底，形成在器件隔离绝缘膜上以在第一方向上延伸的栅电极，形成在硅衬底和栅电极上的第一绝缘膜， 所述第一插塞形成为穿透所述第一绝缘膜，与所述栅极电极和所述第一有源区域重叠，并且在垂直于所述第一方向的第二方向上延伸，穿过所述第二有源区域上方的所述第一绝缘膜的第二插塞， 形成在第一绝缘膜上的第二绝缘膜和埋在第二绝缘膜中的互连，并且形成为沿着第二方向从第一插塞的侧表面退回并且仅覆盖第一插头的上表面的一部分。

公开(公告)号：US20120309143A1

公开(公告)日：2012-12-06

申请号：US13584253

申请日：2012-08-13

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

摘要： A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

摘要翻译： 半导体器件包括其中限定了存储单元的有源区的硅衬底，形成在器件隔离绝缘膜上以在第一方向上延伸的栅电极，形成在硅衬底和栅电极上的第一绝缘膜， 所述第一插塞形成为穿透所述第一绝缘膜，与所述栅极电极和所述第一有源区域重叠，并且在垂直于所述第一方向的第二方向上延伸，穿过所述第二有源区域上方的所述第一绝缘膜的第二插塞， 形成在第一绝缘膜上的第二绝缘膜和埋在第二绝缘膜中的互连，并且形成为沿着第二方向从第一插塞的侧表面退回并且仅覆盖第一插头的上表面的一部分。

公开(公告)号：US07913195B2

公开(公告)日：2011-03-22

申请号：US12026753

申请日：2008-02-06

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L21/00

CPC分类号： H01L21/823456 ,  H01L21/823412 ,  H01L27/0207

摘要： According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor are controlled. An overlapping area of a gate electrode and an element region of a certain group is extracted from mask layout data. The overlapping area is expanded to determine the shape of a mask used in injecting impurity in a channel layer. The data on the mask shape is then added to the mask layout data.

摘要翻译： 根据针对特定工厂设备创建的掩模布局数据，构成半导体器件的晶体管根据栅极长度被分为多个组。 此后，为每组设定引入沟道层的杂质浓度，从而控制晶体管的栅极长度阈值特性。 从掩模布局数据中提取栅极电极和特定组的元件区域的重叠区域。 扩大重叠区域以确定在通道层中注入杂质时使用的掩模的形状。 然后将掩模形状的数据添加到掩模布局数据中。