公开(公告)号：US20110008943A1

公开(公告)日：2011-01-13

申请号：US12885086

申请日：2010-09-17

申请人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.

摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。

公开(公告)号：US20100237404A1

公开(公告)日：2010-09-23

申请号：US12718002

申请日：2010-03-05

申请人： KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US08530958B2

公开(公告)日：2013-09-10

申请号：US12718002

申请日：2010-03-05

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/792

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US20070228446A1

公开(公告)日：2007-10-04

申请号：US11717053

申请日：2007-03-13

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n + + / - 型半导体区域的上表面上形成硅化物层，其存储栅电极MG侧的端部由第二侧壁限定。

公开(公告)号：US07745288B2

公开(公告)日：2010-06-29

申请号：US11717053

申请日：2007-03-13

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US08278169B2

公开(公告)日：2012-10-02

申请号：US12885086

申请日：2010-09-17

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.

摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。

公开(公告)号：US20090001449A1

公开(公告)日：2009-01-01

申请号：US12132609

申请日：2008-06-03

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.

摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。

公开(公告)号：US20100188891A1

公开(公告)日：2010-07-29

申请号：US12676387

申请日：2008-09-08

申请人： Yasuhiro Taniguchi ,  Kosuke Okuyama

发明人： Yasuhiro Taniguchi ,  Kosuke Okuyama

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C14/0081 ,  G11C7/106 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677

摘要： The semiconductor device has: a first magnetoresistance element; a second magnetoresistance element. The first and second magnetoresistance elements each includes a free layer which can be changed in spin orientation therein and a pinned layer which is fixed in spin orientation therein. The first magnetoresistance element is coupled to a first transistor at the free layer, and to a first power-source terminal at the pinned layer. The second magnetoresistance element is coupled to a second transistor at the free layer, and to the first power-source terminal at the pinned layer. In this device, the reliability of stored data is increased by preventing an undesired resistance condition's change in a magnetoresistance memory cell.

摘要翻译： 半导体器件具有：第一磁阻元件; 第二磁阻元件。 第一和第二磁阻元件各自包括可以在其中自旋取向改变的自由层和固定在其中的自旋取向的钉扎层。 第一磁阻元件在自由层处耦合到第一晶体管，并且耦合到钉扎层处的第一电源端子。 第二磁阻元件在自由层处耦合到第二晶体管，并且在被钉扎层处耦合到第一电源端子。 在该装置中，通过防止不期望的电阻条件在磁阻存储单元中的变化来增加存储数据的可靠性。