公开(公告)号：US06326824B1

公开(公告)日：2001-12-04

申请号：US09626963

申请日：2000-07-27

申请人： Koji Hosoe ,  Jun Funaki ,  Toshiyuki Shimizu ,  Michio Numata

发明人： Koji Hosoe ,  Jun Funaki ,  Toshiyuki Shimizu ,  Michio Numata

IPC分类号： H03L700

CPC分类号： H04J3/0682 ,  H04L7/0004 ,  H04L7/08

摘要： An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. When a device receives a system synchronizing signal form another device, the device sets an initial value in a counter. Thereby, the counter value of a counter in a pilot device and counter values of counters in the other devices are made to coincide with each other.

摘要翻译： 考虑到通过导频装置和其他装置之间的信号线发送信号的时间延迟以及在各个装置中引起的处理延迟，初始值产生电路产生初始值。 当设备从另一个设备接收到系统同步信号时，设备在计数器中设置初始值。 由此，导频装置中的计数器的计数值和其他装置中的计数器的计数值相互一致。

公开(公告)号：US5761728A

公开(公告)日：1998-06-02

申请号：US777184

申请日：1996-12-27

申请人： Hiroshi Saito ,  Takatsugu Sasaki ,  Hirohide Sugahara ,  Akira Kabemoto ,  Hajime Takahashi ,  Jun Funaki

发明人： Hiroshi Saito ,  Takatsugu Sasaki ,  Hirohide Sugahara ,  Akira Kabemoto ,  Hajime Takahashi ,  Jun Funaki

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F15/16 ,  G06F9/38

CPC分类号： G06F13/1673

摘要： An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

摘要翻译： 用于计算机系统的异步访问系统包括执行处理的处理模块，至少一个共享系统存储器模块以及连接处理模块和共享系统存储器模块的系统总线。 每个处理模块包括处理器，耦合到处理器和系统总线的多个缓冲器，以及用于将数据从多个处理器写入共享系统存储器模块的控制单元。 通过处理器将数据写入共享系统存储器模块，该处理器产生写入指令以经由多个缓冲器和系统总线写入数据。 控制单元控制写入，使得一个写入指令将数据写入多个缓冲器，然后经由系统总线将数据传送到共享系统存储器模块，另一个写入指令将另外的数据写入另一个多个缓冲器并传送附加的数据 数据到共享系统内存模块。

公开(公告)号：US20050285846A1

公开(公告)日：2005-12-29

申请号：US11158325

申请日：2005-06-22

申请人： Jun Funaki

发明人： Jun Funaki

IPC分类号： G09G5/00

CPC分类号： G06F3/04886 ,  G06F2203/04809 ,  G09B21/004

摘要： Conductivity of a photoconductive layer 420 changes in accordance with a display pattern made of black and white, which is displayed on a display device 200 of a touch panel apparatus with tactile display function 10. With this change of the conductivity, viscosity of an electrorheological fluid layer 430 changes in accordance with this display pattern. This change of the viscosity is presented to an operator, as tactile information corresponding to the display pattern displayed as the visual information.

摘要翻译： 光电导层420的电导率根据由具有触觉显示功能的触摸面板装置的显示装置200上显示的黑白显示图案而变化。 随着电导率的这种变化，电流变流体层430的粘度根据该显示图案而变化。 作为与作为视觉信息显示的显示图案对应的触觉信息，将粘度的这种变化呈现给操作者。

公开(公告)号：US5546363A

公开(公告)日：1996-08-13

申请号：US358725

申请日：1994-12-19

申请人： Jun Funaki ,  Shoji Tenma

发明人： Jun Funaki ,  Shoji Tenma

IPC分类号： G06F1/14 ,  G04G3/02 ,  G04G7/00 ,  G04B17/12

CPC分类号： G04G3/02 ,  G04G7/00

摘要： A commercially available clock IC which is easily influenced by a temperature change or the like is used as it is, thereby easily allowing the clock IC to function as a high precision clock IC. A high precision oscillator is provided separately from a clock circuit as a clock IC. On the basis of a clock signal from the high precision oscillator, a predetermined time, for example, one minute is measured by a high precision clock control circuit. A correction signal is transmitted to the clock circuit as a clock IC from a high precision control circuit every measurement of such a predetermined time, thereby allowing the correcting operation of the time information to be executed. The clock circuit is, consequently, made operative at a precision of the high precision oscillating circuit.

摘要翻译： 容易受到温度变化等的影响的市售时钟IC被直接使用，由此容易地使时钟IC用作高精度时钟IC。 与作为时钟IC的时钟电路分开提供高精度振荡器。 基于来自高精度振荡器的时钟信号，通过高精度时钟控制电路测量例如1分钟的预定时间。 校正信号作为来自高精度控制电路的时钟IC作为时钟电路每测量一次这样的预定时间，从而允许执行时间信息的校正操作。 因此，时钟电路以高精度振荡电路的精度工作。

公开(公告)号：US5905875A

公开(公告)日：1999-05-18

申请号：US592512

申请日：1996-01-26

申请人： Hajime Takahashi ,  Nobuhisa Hattori ,  Toshihide Tsuzuki ,  Jun Funaki

发明人： Hajime Takahashi ,  Nobuhisa Hattori ,  Toshihide Tsuzuki ,  Jun Funaki

IPC分类号： G06F11/18 ,  G06F11/20 ,  G06F13/36 ,  G06F15/16 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F11/2007

摘要： A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.

摘要翻译： 具有提高总线时钟速度同时保持高可靠性和容错性能以及利用当前操作系统资源的能力的多处理器系统。 多处理器系统由通过复制的系统总线连接在一起的多个处理器模块组成。 复制的系统总线被分成多个段，并且这些段通过至少一个总线扩展器机制耦合在一起。 多处理器系统还设置有第一通知装置，其设置在用于控制物理总线的状态的总线控制机构和总线扩展器机构之间，并且总线控制机构和总线扩展器机制通过每个机制的状态相互通知 第一通知手段。

公开(公告)号：US5737573A

公开(公告)日：1998-04-07

申请号：US733721

申请日：1996-10-16

申请人： Jun Funaki ,  Akira Kabemoto ,  Hirohide Sugahara

发明人： Jun Funaki ,  Akira Kabemoto ,  Hirohide Sugahara

IPC分类号： G06F15/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/16 ,  G06F13/36 ,  G06F15/177 ,  G06F12/12

CPC分类号： G06F12/0815

摘要： An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit. The first connection unit within the processing module comprises an internal bus, an internal buffer storing data read from the shared memory module, a system bus control circuit coupled to the system bus, an internal bus control circuit coupled to the central processing unit via the internal bus, and an internal buffer control circuit controlling write/read of the internal buffer based on a signal from the internal bus control circuit. One of the internal buffer control circuit and the internal bus control circuit invalidates a content of the internal buffer when one of a plurality of invalidating conditions is satisfied.

摘要翻译： 异步访问系统包括系统总线，至少一个具有主存储器的处理模块，中央处理单元和连接到系统总线的第一连接单元，以及至少一个设有共享存储单元的共享存储器模块， 连接到系统总线的第二连接单元。 当第一连接单元识别从中央处理单元请求的共享存储器模块的读取时，处理模块内的第一连接单元经由系统总线向共享存储器模块发送块读请求。 处理模块内的第一连接单元包括内部总线，存储从共享存储器模块读取的数据的内部缓冲器，耦合到系统总线的系统总线控制电路，经由内部耦合到中央处理单元的内部总线控制电路 总线和内部缓冲器控制电路，其基于来自内部总线控制电路的信号来控制内部缓冲器的写入/读取。 当满足多个无效条件中的一个时，内部缓冲器控制电路和内部总线控制电路之一使内部缓冲器的内容无效。

公开(公告)号：US5346772A

公开(公告)日：1994-09-13

申请号：US53648

申请日：1993-04-27

申请人： Shuzo Akiyama ,  Kenichiro Nakashima ,  Kunio Imai ,  Ryuji Murayama ,  Jun Funaki

发明人： Shuzo Akiyama ,  Kenichiro Nakashima ,  Kunio Imai ,  Ryuji Murayama ,  Jun Funaki

IPC分类号： C09K11/06 ,  H05B33/14 ,  B32B9/00

CPC分类号： C09K11/06 ,  H05B33/14 ,  Y10S428/917 ,  Y10T428/31678

摘要： An organic electroluminescent device comprises an anode, a positive-hole transport layer of organic compound, an emitting layer of organic compound, and a cathode which are laminated in sequence, wherein the emitting layer comprises a pyrimidopyrimidine derivative. This device emits with a high luminance and high emission efficiency.

摘要翻译： 有机电致发光器件包括阳极，有机化合物的正空穴传输层，有机化合物的发光层和阴极，其顺序层叠，其中发光层包含嘧啶并嘧啶衍生物。 该器件以高亮度和高发光效率发射。

公开(公告)号：US07589714B2

公开(公告)日：2009-09-15

申请号：US11158325

申请日：2005-06-22

申请人： Jun Funaki

发明人： Jun Funaki

IPC分类号： G06F3/041 ,  G06F3/042

CPC分类号： G06F3/04886 ,  G06F2203/04809 ,  G09B21/004

摘要： Conductivity of a photoconductive layer changes in accordance with a display pattern made of black and white, which is displayed on a display device of a touch panel apparatus with tactile display function. With this change of the conductivity, viscosity of an electrorheological fluid layer changes in accordance with this display pattern. This change of the viscosity is presented to an operator, as tactile information corresponding to the display pattern displayed as the visual information.

摘要翻译： 光电导层的电导率根据由触摸显示功能的触摸面板装置的显示装置显示的黑白显示图案而变化。 随着电导率的变化，电流变流体层的粘度根据该显示图案而变化。 作为与作为视觉信息显示的显示图案对应的触觉信息，将粘度的这种变化呈现给操作者。

公开(公告)号：US06791277B2

公开(公告)日：2004-09-14

申请号：US09799123

申请日：2001-03-06

申请人： Jun Funaki ,  Satoshi Miyaguchi ,  Yoshiyuki Okuda ,  Yoshihiro Ushigusa ,  Masami Tsuchida

发明人： Jun Funaki ,  Satoshi Miyaguchi ,  Yoshiyuki Okuda ,  Yoshihiro Ushigusa ,  Masami Tsuchida

IPC分类号： H05B3300

CPC分类号： H01L27/3281 ,  H01L51/0059 ,  H01L51/0081 ,  H01L51/0583 ,  H01L2251/308

摘要： A light emitting element capable of suppressing the deterioration of an organic thin film layer as light emitting layers is provided. The light emitting element comprises a light emitting body emitting light by impressing voltage and a rectifier connected in series with the light emitting body, the light emitting body contains the NPB thin film layer, and the rectifier has the NPB thin film layer.

摘要翻译： 提供能够抑制作为发光层的有机薄膜层劣化的发光元件。 发光元件包括通过施加电压发光的发光体和与发光体串联连接的整流器，发光体包含NPB薄膜层，整流器具有NPB薄膜层。

公开(公告)号：US5796996A

公开(公告)日：1998-08-18

申请号：US502351

申请日：1995-07-14

申请人： Shoji Temma ,  Jun Funaki

发明人： Shoji Temma ,  Jun Funaki

IPC分类号： G06F12/16 ,  G06F9/38 ,  G06F9/48 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3861 ,  G06F9/3834

摘要： In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer, thereby completing the write instruction. Prior to executing a read instruction subsequent to the write instruction, the write address and the write data of the output buffer are transferred to a sync buffer and are stored into a write address holding register and a write data holding register. Further, a using state display register is set into the holding state. When the CPU executes the read instruction, the write data of the write data holding register is written into the memory mapped register and the end of the writing operation is synchronized with the end of the read instruction. When the sync buffer unit receives an interruption instruction in the holding state, an interruption return instruction address is returned to an address of the write instruction of the data in the holding state. The process is restarted from the write instruction of the memory mapped register by the control program by the end of the interruption.

摘要翻译： 在CPU执行外部存储器的存储器映射寄存器的控制程序的写入指令的情况下，将写入地址和写入数据写入输出缓冲器，从而完成写入指令。 在执行写入指令之后的读取指令之前，将输出缓冲器的写入地址和写入数据传送到同步缓冲器，并将其存储到写入地址保持寄存器和写入数据保持寄存器中。 此外，将使用状态显示寄存器设置为保持状态。 当CPU执行读取指令时，写入数据保持寄存器的写入数据被写入存储器映射寄存器，并且写入操作的结束与读取指令的结束同步。 当同步缓冲器单元接收到处于保持状态的中断指令时，中断返回指令地址返回到保持状态下的数据的写入指令的地址。 在中断结束时，控制程序从存储器映射寄存器的写入指令重新开始该过程。