公开(公告)号：US07710172B2

公开(公告)日：2010-05-04

申请号：US12169972

申请日：2008-07-09

申请人： Koji Kuroki ,  Yasuhiro Takai ,  Hiroki Fujisawa

发明人： Koji Kuroki ,  Yasuhiro Takai ,  Hiroki Fujisawa

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

摘要翻译： DLL电路包括延迟线（CDL）（10），延迟线（10）以相对粗调的音调延迟时钟信号，延迟线（FDL）（20），以相当精细的调节间距延迟时钟信号;以及相位检测电路 以及控制延迟线（10,20）的延迟量的计数器控制电路。 计数器控制电路通过线性搜索方法控制延迟线（10），并通过二进制搜索方法来控制延迟线（20）。 结果，即使当用于调整延迟线（20）的计数信号的位数增加时，也可以高速地确定延迟量。

公开(公告)号：US07580321B2

公开(公告)日：2009-08-25

申请号：US12071198

申请日：2008-02-19

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

摘要翻译： 本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

公开(公告)号：US20070091714A1

公开(公告)日：2007-04-26

申请号：US11583980

申请日：2006-10-20

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

摘要翻译： 本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

公开(公告)号：US20080165611A1

公开(公告)日：2008-07-10

申请号：US12071198

申请日：2008-02-19

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

公开(公告)号：US07345950B2

公开(公告)日：2008-03-18

申请号：US11583980

申请日：2006-10-20

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

摘要翻译： 本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

公开(公告)号：US20080040567A1

公开(公告)日：2008-02-14

申请号：US11882425

申请日：2007-08-01

申请人： Koji Kuroki ,  Shuichi Kubouchi ,  Hiroki Fujisawa

发明人： Koji Kuroki ,  Shuichi Kubouchi ,  Hiroki Fujisawa

IPC分类号： G11C7/22 ,  G06F12/00

CPC分类号： G11C7/1078 ,  G06F12/0862 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/107

摘要： A command control circuit includes a read-clock generation circuit that generates a read clock ICLK-R at the time of reading, a write-clock generation circuit that generates a write clock ICLK-W at the time of writing, and a burst chop AL counter that counts an additive latency of a burst chop command. The burst chop AL counter counts the burst chop command in synchronization with both the read clock ICLK-R and the write clock ICLK-W. This eliminates a need of separately arranging an AL counter that counts the burst chop command at the time of reading and an AL counter that counts the burst chop command at the time of writing.

摘要翻译： 命令控制电路包括读取时产生读时钟ICLK-R的读时钟产生电路，写入时产生写时钟ICLK-W的写时钟生成电路和突发脉冲串AL 计数器计数突发斩波命令的附加延迟。 突发脉冲串AL计数器与读时钟ICLK-R和写入时钟ICLK-W同步地计数脉冲串猝发命令。 这消除了在读取时单独排列计数突发斩指令的AL计数器和在写入时对突发斩波指令进行计数的AL计数器的需要。

公开(公告)号：US20070046354A1

公开(公告)日：2007-03-01

申请号：US11511352

申请日：2006-08-29

申请人： Koji Kuroki ,  Hiroki Fujisawa

发明人： Koji Kuroki ,  Hiroki Fujisawa

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： Disclosed is a delay adjustment circuit including a first set of transistors, which are connected between a PMOS transistor forming an inverter and a power supply in parallel and have gates supplied with control signals, respectively, a second set of transistors which are connected between an NMOS transistor forming the inverter, and the ground GND, in parallel and have gates supplied with control signals, respectively, and another inverter receiving an output of the inverter as an input. At least one of the transistors of the first set of transistors and at least one of the transistors of the second set of transistors are set in an on-state.

摘要翻译： 公开了一种延迟调整电路，包括第一组晶体管，它们分别连接在形成逆变器的PMOS晶体管和电源并联并且分别具有控制信号的栅极之间，第二组晶体管连接在NMOS 形成逆变器的晶体管和地GND并联并且分别具有控制信号的栅极，另一个反相器接收反相器的输出作为输入。 第一组晶体管的晶体管中的至少一个晶体管和第二组晶体管的至少一个晶体管被设置为导通状态。

公开(公告)号：US08633758B2

公开(公告)日：2014-01-21

申请号：US13064237

申请日：2011-03-11

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Hitoshi Tanaka

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Hitoshi Tanaka

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F1/46 ,  G11C5/145 ,  H02M1/15 ,  H02M3/07 ,  H02M2001/0045

摘要： A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.

摘要翻译： 一种半导体器件包括：升压电路，其根据外部电源电压升压升压范围内的内部电源电压;将外部电源电压与规定的基准电压进行比较的外部电压电平比较电路;以及可变电阻器 电路包括连接到升压电路的输出端子的可变电阻器。 可变电阻电路基于外部电压电平比较电路的比较结果来控制可变电阻器的电阻值。

公开(公告)号：US08630129B2

公开(公告)日：2014-01-14

申请号：US13304062

申请日：2011-11-23

申请人： Hiroki Fujisawa ,  Yuuji Motoyama

发明人： Hiroki Fujisawa ,  Yuuji Motoyama

IPC分类号： G11C7/10

CPC分类号： G11C11/4087 ,  G11C11/4096 ,  G11C11/4097

摘要： A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.

摘要翻译： 半导体器件设置有控制电路，该控制电路产生多个第一控制信号，该第一控制信号指示列开关在读取时导通的定时;以及多个第二控制信号，其指示列开关在写入时进行的定时。 控制电路激活多个第一控制信号，使得在从外部接收到读指令之后从每个存储单元阵列读取的数据到达FIFO电路的定时在每个存储体中相同，并激活多个第二控制 信号使得列开关匹配从外部输入到第一数据输入/输出端的写入数据到达对应的列开关的定时。

公开(公告)号：US08553489B2

公开(公告)日：2013-10-08

申请号：US13317601

申请日：2011-10-24

申请人： Hiroki Fujisawa ,  Yuuji Motoyama

发明人： Hiroki Fujisawa ,  Yuuji Motoyama

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C8/18 ,  G11C11/408

摘要： For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.

摘要翻译： 例如，半导体器件包括锁存电路，其输入节点连接到输入选择电路，其输出节点连接到输出选择电路; 以及控制电路，其控制输入选择电路和输出选择电路。 控制电路包括用于产生输入指针信号的移位寄存器和产生输出指针信号的二进制计数器。 输入选择电路基于输入指针信号的值选择一个锁存电路。 输出选择电路根据输出指针信号的值选择一个锁存电路。 因此，可以防止在输入选择电路中发生危险，并且可以减少发送输出指针信号的信号线的数量。