公开(公告)号：US20110298039A1

公开(公告)日：2011-12-08

申请号：US13207149

申请日：2011-08-10

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层和形成在第二绝缘层上的控制电极 绝缘层。 第二绝缘层包括在电荷存储层上形成的第一氧化硅膜，形成在第一氧化硅膜上的氮化硅膜，形成在氮化硅膜上的金属氧化物膜，以及形成在金属氧化物膜上的氮化物膜 。 金属氧化物膜的相对介电常数不小于7。

公开(公告)号：US08008707B2

公开(公告)日：2011-08-30

申请号：US12333983

申请日：2008-12-12

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层和形成在第二绝缘层上的控制电极 绝缘层。 第二绝缘层包括在电荷存储层上形成的第一氧化硅膜，形成在第一氧化硅膜上的氮化硅膜，形成在氮化硅膜上的金属氧化物膜，以及形成在金属氧化物膜上的氮化物膜 。 金属氧化物膜的相对介电常数不小于7。

公开(公告)号：US08791521B2

公开(公告)日：2014-07-29

申请号：US13423664

申请日：2012-03-19

申请人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.

摘要翻译： 半导体器件包括在电荷存储层和控制电极层之间形成的电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括：第一堆叠，其包括介于第一和第二氧化硅膜之间的第一氮化硅膜或高介电常数膜，或包括第二高介电常数膜和第三氧化硅膜的第二堆叠， 形成在控制电极层和第一或第二堆叠之间的第二氮化硅膜。 在第三区域中，第二氮化硅膜比第一区域相对薄。

公开(公告)号：US20090152618A1

公开(公告)日：2009-06-18

申请号：US12333983

申请日：2008-12-12

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层，形成在第二绝缘层上的控制电极 层。 第二绝缘层包括第一氧化硅膜，形成在第一氧化硅膜上并具有不小于7的相对介电常数的中间绝缘膜和形成在中间绝缘膜上的第二氧化硅膜。 至少在第一或第二氧化硅膜或第一氧化硅膜和中间绝缘膜之间的边界或第二氧化硅膜和中间绝缘膜之间的边界上形成电荷陷阱层。

公开(公告)号：US08742487B2

公开(公告)日：2014-06-03

申请号：US13207149

申请日：2011-08-10

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer and including a first high dielectric insulating film which has a higher relative permittivity than a silicon nitride film and a second high dielectric insulating film which has a higher relative permittivity than a silicon nitride film, the first and second high dielectric insulating films being structured so that a silicon oxide film is interposed between them, a control electrode formed on the second insulation layer, a first portion formed between the charge storage layer and the second insulation layer and containing silicon and nitrogen, and a second portion containing silicon and oxygen and located between the charge storage layer and the second insulation layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层，并且包括第一高介电绝缘膜， 具有比氮化硅膜更高的相对介电常数的相对介电常数和比氮化硅膜具有更高的相对介电常数的第二高介电绝缘膜，第一和第二高介电绝缘膜被构造成在它们之间插入氧化硅膜， 形成在所述第二绝缘层上的控制电极，形成在所述电荷存储层和所述第二绝缘层之间并且包含硅和氮的第一部分，以及位于所述电荷存储层和所述第二绝缘层之间的含有硅和氧的第二部分 。

公开(公告)号：US08471326B2

公开(公告)日：2013-06-25

申请号：US13049573

申请日：2011-03-16

申请人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L21/762 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.

摘要翻译： 根据一个实施例，半导体衬底包括单元区域和外围电路区域，在单元区域和外围电路区域中的半导体衬底上形成第一电介质膜，在第一电介质膜上形成第一导电膜 单元区域和外围电路区域，在单元区域中的第一导电膜上形成第一导电膜电介质膜，在外围电路的第一导电膜上形成第二导电膜电介质膜 区域，其膜厚度大于第一导电膜电介质膜，并且第二导电膜形成在电池区域中的第一导电膜电介质膜上，第二导电膜电介质膜 在外围电路区域。

公开(公告)号：US20130069135A1

公开(公告)日：2013-03-21

申请号：US13423664

申请日：2012-03-19

申请人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.

摘要翻译： 半导体器件包括在电荷存储层和控制电极层之间形成的电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括：第一堆叠，其包括介于第一和第二氧化硅膜之间的第一氮化硅膜或高介电常数膜，或包括第二高介电常数膜和第三氧化硅膜的第二堆叠， 形成在控制电极层和第一或第二堆叠之间的第二氮化硅膜。 在第三区域中，第二氮化硅膜比第一区域相对薄。

公开(公告)号：US20120049258A1

公开(公告)日：2012-03-01

申请号：US13049573

申请日：2011-03-16

申请人： Koji NAKAHARA ,  Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Koji NAKAHARA ,  Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.

摘要翻译： 根据一个实施例，半导体衬底包括单元区域和外围电路区域，在单元区域和外围电路区域中的半导体衬底上形成第一电介质膜，在第一电介质膜上形成第一导电膜 单元区域和外围电路区域，在单元区域中的第一导电膜上形成第一导电膜电介质膜，在外围电路的第一导电膜上形成第二导电膜电介质膜 区域，其膜厚度大于第一导电膜电介质膜，并且第二导电膜形成在电池区域中的第一导电膜电介质膜上，第二导电膜电介质膜 在外围电路区域。

公开(公告)号：US08525252B2

公开(公告)日：2013-09-03

申请号：US13233788

申请日：2011-09-15

申请人： Kenichiro Toratani ,  Masayuki Tanaka ,  Kazuhiro Matsuo

发明人： Kenichiro Toratani ,  Masayuki Tanaka ,  Kazuhiro Matsuo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.

公开(公告)号：US20100308393A1

公开(公告)日：2010-12-09

申请号：US12722111

申请日：2010-03-11

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/40114

摘要： A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film.

摘要翻译： 一种半导体器件，包括具有通过元件隔离绝缘膜隔离的有源区的半导体衬底; 形成在位于有源区上的栅极绝缘膜上的浮栅电极膜; 在所述元件隔离绝缘膜的上表面上方形成的电极间绝缘膜，以及所述浮栅电极膜的上表面和侧壁，所述电极间绝缘膜由多层膜构成，所述多个膜层包括介电常数等于或等于 大于氮化硅膜; 形成在电极间绝缘膜上的控制栅极电极膜; 以及在所述浮栅电极膜的上表面和所述电极间绝缘膜之间形成的氧化硅膜; 其中，电极间绝缘膜的高电介质膜与浮栅电极膜的侧壁直接接触。