-
公开(公告)号：US20060227629A1
公开(公告)日：2006-10-12
申请号：US11378444
申请日：2006-03-16
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译： 访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测列地址CADD，突发地址和更新字之后读出存储的数据 行新选择存储单元MC。 在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。 在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在 分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。 操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。 为每个访问操作选择合适的操作条件。
-
公开(公告)号：US07321515B2
公开(公告)日：2008-01-22
申请号：US11378444
申请日：2006-03-16
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译： 访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测到列地址CADD，突发地址和更新单词之后读出存储的数据 行新选择存储单元MC。 在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。 在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在 分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。 操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。 为每个访问操作选择合适的操作条件。
-
公开(公告)号：US06917541B2
公开(公告)日：2005-07-12
申请号：US10060185
申请日：2002-02-01
申请人： Koji Shimbayashi , Takaaki Furuyama
发明人： Koji Shimbayashi , Takaaki Furuyama
摘要： This invention provides a nonvolatile semiconductor memory device including a novel memory core portion in which an influence of a parasitic element component in a memory cell information reading path is excluded in a reading operation, and novel sensing means accompanying this memory core structure, so as to achieve rapid sensing. In the memory core portion, a selected memory cell is selected by a global bit line through a local bit line and an adjacent global bit line is connected to a local bit line in a non-selected sector. A column selecting portion connects a pair of the global bit lines to a pair of data bus lines. A load portion having a load equivalent to a parasitic capacitance of a path leading from the memory cell and for supplying a reference current to a reference side is connected to a pair of the data bus lines. A current of the memory cell information is compared with the reference current by a current comparing portion and a differential current is outputted. A path load is equalized by a pair of adjacent paths so that an effect from noise is canceled, thus making it possible to achieve rapid reading.
摘要翻译： 本发明提供了一种非易失性半导体存储器件，其包括新颖的存储器芯部分，其中在读取操作中排除了存储器单元信息读取路径中的寄生元件分量的影响，以及伴随该存储器核心结构的新型感测装置， 实现快速感知。 在存储器核心部分中，通过局部位线的全局位线选择选定的存储单元，并且相邻的全局位线连接到非选择扇区中的本地位线。 列选择部分将一对全局位线连接到一对数据总线。 具有与从存储单元引出的路径的寄生电容相当并且用于向参考侧提供参考电流的负载的负载部分连接到一对数据总线。 通过电流比较部分将存储单元信息的电流与参考电流进行比较，并输出差分电流。 路径负载由一对相邻的路径相等，从而消除噪声的影响，从而可以实现快速读取。
-
4.发明授权Method and apparatus for address allotting and verification in a semiconductor device 有权用于半导体器件中的地址分配和验证的方法和装置公开(公告)号：US07433219B2
公开(公告)日：2008-10-07
申请号：US11341029
申请日：2006-01-27
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
-
5.发明申请Method and apparatus for address allotting and verification in a semiconductor device 有权用于半导体器件中的地址分配和验证的方法和装置公开(公告)号：US20060209583A1
公开(公告)日：2006-09-21
申请号：US11341029
申请日：2006-01-27
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
-
6.发明授权Method and apparatus for address allotting and verification in a semiconductor device 有权用于半导体器件中的地址分配和验证的方法和装置公开(公告)号：US07813154B2
公开(公告)日：2010-10-12
申请号：US12199684
申请日：2008-08-27
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
-
7.发明授权Method and apparatus for address allotting and verification in a semiconductor device 有权用于半导体器件中的地址分配和验证的方法和装置公开(公告)号：US08023341B2
公开(公告)日：2011-09-20
申请号：US12903065
申请日：2010-10-12
IPC分类号： G11C7/10
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
-
8.发明申请METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE 有权用于在半导体器件中寻址和验证的方法和装置公开(公告)号：US20080316787A1
公开(公告)日：2008-12-25
申请号：US12199684
申请日：2008-08-27
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
-
公开(公告)号：US08031537B2
公开(公告)日：2011-10-04
申请号：US12987466
申请日：2011-01-10
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
-
公开(公告)号：US20060002196A1
公开(公告)日：2006-01-05
申请号：US11173735
申请日：2005-07-01
申请人： Takaaki Furuyama , Satoru Kawamoto
发明人： Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C7/10
摘要： A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.
摘要翻译： 存储器系统（1A）包括存储器部分（2A）和存储器控制部分（3A）。 存储部分（2A）包括测试电路（4A），数据寄存器（5A），数据输出部分（6A）和存储器核心部分（9A）。 数据DI保存在数据电阻（5A）中。 测试电路（4A）响应于测试信号TEST将写入禁止信号WINH输出到存储器芯部分（9A）。 识别写入指令被输入到存储部分（2A）和选择信号S的写指令识别信号WR被反转，并且作为响应，数据寄存器（5A）的保留数据DR被输出作为输出数据DO 从数据输出部分（6A）。 因此，可以测试写命令CMD和数据DI的生成，传播或识别操作是否正常，而不执行将数据写入存储器部分的存储单元的操作。
-
-
-
-
-
-
-
-
-
搜索结果
45 条记录 (耗时 0.02 秒)
