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公开(公告)号：US20210006253A1
公开(公告)日：2021-01-07
申请号：US16836723
申请日：2020-03-31
Inventor： Chul Woo KIM , Hyun Su PARK
Abstract: A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.
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公开(公告)号：US20200366295A1
公开(公告)日：2020-11-19
申请号：US16703748
申请日：2019-12-04
Inventor： Chul Woo KIM , Hyun Su PARK
Abstract: Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.
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公开(公告)号：US20180159552A1
公开(公告)日：2018-06-07
申请号：US15482500
申请日：2017-04-07
Inventor： Chul Woo KIM , Sung Jun MOON , Sang Su LEE
CPC classification number: H03M13/03 , G06F3/0659 , G06F9/30087 , H03K19/17744 , H03M13/1105 , H04L1/004
Abstract: A receiver for data communication may include: an input buffer suitable for generating plural comparison signals by differentially comparing plural input signals; a de-serializer suitable for generating plural groups of de-serialized signals by de-serializing the plural comparison signals at a preset de-serialization ratio; a D flip-flop suitable for generating plural delayed signals by delaying last de-serialized signals of the respective plural groups of de-serialized signals by a preset time; a symbol decoder suitable for comparing current and previous states of the plural comparison signals and for generating plural symbol signals based on a preset state diagram defining a correspondence relationship between the plural symbol signals and changes between current and previous states of the plural comparison signals.
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公开(公告)号：US20180156870A1
公开(公告)日：2018-06-07
申请号：US15650403
申请日：2017-07-14
Inventor： Chul Woo KIM , Dong Yoon KIM , In Hwa JUNG , Yong Ju KIM
IPC: G01R31/319 , G01R31/28 , G06F11/22 , G01R31/3167
CPC classification number: G01R31/31905 , G01R31/286 , G01R31/2879 , G01R31/3167 , G01R31/31922 , G01R31/31926 , G06F11/22
Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.
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公开(公告)号：US20220308611A1
公开(公告)日：2022-09-29
申请号：US17465029
申请日：2021-09-02
Inventor： Chul Woo KIM , Jun Young MAENG , In Ho PARK , Jin Woo JEON , Hyun Jin KIM
Abstract: Disclosed is a digital LDO regulator capable of performing asynchronous binary search using a binary-weighted PMOS array. The digital LDO regulator includes a PMOS array unit including a binary-weighted PMOS array and that binary searches the PMOS array asynchronously, and a mode determining unit that operates in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit.
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Patent Agency Ranking
公开(公告)号：US20200052796A1
公开(公告)日：2020-02-13
申请号：US16362066
申请日：2019-03-22
Inventor： Chul Woo KIM , Hyun Su PARK , Jin Cheol SIM , Choong Hwan LEE
Abstract: An optical receiver includes a transimpedance amplifier that converts a current signal corresponding to an optical signal into a voltage signal. The transimpedance amplifier includes an input terminal receiving the current signal, an output terminal outputting the voltage signal, an inverting circuit including a pull-up device that pull-up drives the voltage signal of the output terminal according to the current signal, and a pull-down device that pull-down drives the voltage signal of the output terminal according to the current signal, a feedback resistor electrically connected between the input and output terminals, a first resistor electrically connected between the input terminal and the pull-up device, and a second resistor electrically connected between the input terminal and the pull-down device.
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公开(公告)号：US20160079791A1
公开(公告)日：2016-03-17
申请号：US14591786
申请日：2015-01-07
Inventor： Chul Woo KIM , Min Seob SHIM , Jun Won JUNG , Jung Moon KIM
CPC classification number: H02J7/345
Abstract: Disclosed is an energy harvesting apparatus. The energy harvesting apparatus includes a rectifier for rectifying an alternating current (AC) voltage supplied from an energy source into a direct current (DC) voltage, a charging unit for storing an output voltage of the rectifier, and a maximum power point tracker selectively connected between the rectifier and the charging unit, for differentiating the output voltage of the rectifier in a first connection state, and for controlling the output voltage of the rectifier based on a differentiation result.
Abstract translation: 公开了一种能量收集装置。 能量收集装置包括整流器，用于将从能量源提供的交流（AC）电压整流为直流（DC）电压，用于存储整流器的输出电压的充电单元和选择性地连接的最大功率点跟踪器 在整流器和充电单元之间，用于在整流器的第一连接状态下区分输出电压，并且用于基于微分结果来控制整流器的输出电压。
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公开(公告)号：US20220021392A1
公开(公告)日：2022-01-20
申请号：US17167368
申请日：2021-02-04
Inventor： Chul Woo KIM , Yoon Jae CHOI
Abstract: A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock.
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公开(公告)号：US20200007240A1
公开(公告)日：2020-01-02
申请号：US16565260
申请日：2019-09-09
Inventor： Chul Woo KIM , Sang Geun BAE , Hyun Su PARK , Choong Hwan LEE
Abstract: An optical transceiver includes an optical transmitter and an optical receiver. The optical transmitter includes a laser diode configured to convert a current signal into an optical signal; a main driver comprising first and second output terminals that have a differential structure, the main driver configured to drive the first and second output terminals in response to differential input signals and to provide the current signal to the laser diode through the first output terminal; and an impedance balancer configured to match impedances of the first and second output terminals by adjusting the impedance of the second output terminal according to signal states of the first and second output terminals.
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公开(公告)号：US20200007239A1
公开(公告)日：2020-01-02
申请号：US16565222
申请日：2019-09-09
Inventor： Chul Woo KIM , Sang Geun BAE , Hyun Su PARK , Choong Hwan LEE
Abstract: An optical transceiver includes an optical transmitter and an optical receiver. The optical transmitter includes a laser diode configured to convert a current signal into an optical signal; a main driver comprising first and second output terminals that have a differential structure, the main driver configured to drive the first and second output terminals in response to differential input signals and to provide the current signal to the laser diode through the first output terminal; and an impedance balancer configured to match impedances of the first and second output terminals by adjusting the impedance of the second output terminal according to signal states of the first and second output terminals.
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