公开(公告)号：US06100720A

公开(公告)日：2000-08-08

申请号：US287582

申请日：1999-04-06

申请人： Kouichi Kumagai ,  Hiroaki Iwaki

发明人： Kouichi Kumagai ,  Hiroaki Iwaki

IPC分类号： H03K17/693 ,  H03K5/151 ,  H03K19/00 ,  H03K19/0948

CPC分类号： H03K19/0019 ,  H03K5/151

摘要： An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

摘要翻译： 逆变器电路具有用于接收互补输入信号的第一和第二输入端子，用于输出从互补输入信号产生的互补输出信号的第一和第二输出端子，以及一对整流器部分， 输出端子的电位侧到输出端子的较低电位，以节省功耗。

公开(公告)号：US06404254B2

公开(公告)日：2002-06-11

申请号：US09166585

申请日：1998-10-06

申请人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

发明人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

IPC分类号： H03K3286

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356173

摘要： A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side. In addition, the control signals are very few, and a fine timing control for changing over the mode is no longer required.

摘要翻译： 一种半导体集成电路，其被配置为在备用模式中停止向逻辑电路供电，从而实现低功耗，包括锁存电路，其特征在于，作为控制信号，时钟信号在主动 模式，并且在备用模式下提供用于创建信息保持条件的信号，并且施加控制信号的MOSFET包括具有高阈值的第一导电型MOSFET和具有低阈值的第二导电类型MOSFET， 控制信号的幅度大于电源电压。 可以实现半导体集成电路，即主动模式中的高速操作和待机模式中的低功耗彼此兼容，并且如果用于逻辑电路的电源开关仅插入到 高电平电源电压侧和低电平电源电压线一侧。 此外，控制信号非常少，并且不再需要用于改变模式的精细定时控制。

公开(公告)号：US06255862B1

公开(公告)日：2001-07-03

申请号：US09502231

申请日：2000-02-11

申请人： Kouichi Kumagai ,  Hiroaki Iwaki

发明人： Kouichi Kumagai ,  Hiroaki Iwaki

IPC分类号： H03F345

CPC分类号： G11C7/065

摘要： A latch type sense amplifier circuit comprises first and second latch circuits which output the same output signals when a potential difference between a bit line pair is equal to or greater than a predetermined value. The first and second latch circuits output different output signals when the potential difference between the bit line pair is less than the predetermined value. The latch type sense amplifier circuit further comprises a comparison result signal generating circuit which compares the output signals from the first and second latch circuits and outputs a signal indicative of the comparison result.

摘要翻译： 锁存型读出放大器电路包括当位线对之间的电位差等于或大于预定值时输出相同输出信号的第一和第二锁存电路。 当位线对之间的电位差小于预定值时，第一和第二锁存电路输出不同的输出信号。 锁存型读出放大器电路还包括比较结果信号发生电路，其比较来自第一和第二锁存电路的输出信号，并输出指示比较结果的信号。

公开(公告)号：US06208170B1

公开(公告)日：2001-03-27

申请号：US09286029

申请日：1999-04-05

申请人： Hiroaki Iwaki ,  Kouichi Kumagai

发明人： Hiroaki Iwaki ,  Kouichi Kumagai

IPC分类号： H03K19094

CPC分类号： G11C5/14

摘要： A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

摘要翻译： 半导体集成电路包括具有全局源极线VCC，源极开关晶体管耦合到VCC的局部源极线QVCC和全局接地线VSS，低阈值逻辑（组合）电路的电源电路，其连接在QVCC和 VSS和连接在VCC和VSS之间的数据存储（顺序）电路。 数据存储电路包括用于从逻辑电路接收数据的低阈值输入部分和用于锁存由输入部分接收的数据的高阈值锁存部分。 模式开关晶体管插入在低阈值逻辑电路和VSS之间，低阈值输入部分和VCC之间以及低阈值输入部分和VSS之间，用于实现半导体集成电路的睡眠模式。 降低电路规模可以保持低功耗。

公开(公告)号：US5998879A

公开(公告)日：1999-12-07

申请号：US17960

申请日：1998-02-03

申请人： Hiroaki Iwaki ,  Kouichi Kumagai

发明人： Hiroaki Iwaki ,  Kouichi Kumagai

IPC分类号： H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L27/1108 ,  H01L27/1203

摘要： In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of the drain and source diffusion layer regions of the first and second MOS transistors are respectively arranged to be adgacent to each other and are electrically connected to each other, respectively, through a diffusion layer interconnection.

摘要翻译： 在形成在SOI衬底上并包括具有第一和第二NMOS和PMOS晶体管的触发器的CMOS SRAM单元中，具有第一和第二MOS晶体管的传输门和字线部分，其特征在于：字线部分沿着 预定方向; 第一和第二NMOS和PMOS晶体管的源极和漏极扩散层区域沿着预定方向排列，并且这些NMOS和PMOS晶体管的栅极在垂直于预定方向的方向上布置在沟道区域上; 第一和第二NMOS晶体管的栅极分别电连接到第一和第二PMOS晶体管的栅极; 并且在沟道区上的第一和第二NMOS晶体管的栅极和沟道区上的第一和第二PMOS晶体管的栅极之间的区域中，fisrt和第二NMOS和PMOS晶体管的漏极扩散层区域中的每一个， 并且第一和第二MOS晶体管的漏极和源极扩散层区域中的每一个分别布置成彼此相邻并且分别通过扩散层互连彼此电连接。

公开(公告)号：US6134154A

公开(公告)日：2000-10-17

申请号：US281215

申请日：1999-03-30

申请人： Hiroaki Iwaki ,  Kouichi Kumagai

发明人： Hiroaki Iwaki ,  Kouichi Kumagai

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C8/16 ,  G11C11/419

摘要： In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a plurality of word lines and is connected to one of a plurality of bit lines such that a plurality of columns are formed from the plurality of memory cells. A word line selecting section selects one of the plurality of word lines based on a first address. A first column selector selects one of the plurality of columns as a first column based on the first address. A second column selector selects another one of the plurality of columns as a second column based on a second address. An address data of a predetermined portion of the first address is not equal to an address data of the second address. An input/output section includes a first sense amplifier and a first buffer. A first read operation is performed to a first memory cell connected to the selected word line and the first column through the first sense amplifier and the first column selector and a first write operation is performed to a second memory cell connected to the selected word line and the second column through the first buffer and the second column selector.

摘要翻译： 在半导体存储器件中，多个存储单元被布置成矩阵。 多个存储单元中的每一个连接到多个字线中的一个，并且连接到多个位线中的一个，使得从多个存储单元形成多个列。 字线选择部分基于第一地址来选择多个字线之一。 第一列选择器基于第一地址选择多个列之一作为第一列。 第二列选择器基于第二地址选择多个列中的另一列作为第二列。 第一地址的预定部分的地址数据不等于第二地址的地址数据。 输入/输出部分包括第一读出放大器和第一缓冲器。 通过第一读出放大器和第一列选择器对连接到所选字线和第一列的第一存储单元执行第一读操作，并且对连接到所选字线的第二存储单元执行第一写操作，并且 第二列通过第一缓冲区和第二列选择器。

公开(公告)号：US06505717B2

公开(公告)日：2003-01-14

申请号：US09940598

申请日：2001-08-29

申请人： Kouichi Kumagai ,  Kazuyoshi Miyachi ,  Tadao Isobe ,  Hideyuki Ooishi

发明人： Kouichi Kumagai ,  Kazuyoshi Miyachi ,  Tadao Isobe ,  Hideyuki Ooishi

IPC分类号： F16D6900

CPC分类号： F16D43/18

摘要： In a clutch weight for a wet centrifugal clutch, a weight member 14 is formed of a sintered metal. Thus, the cost can be reduced, while stabilizing the clutch performance and enhancing the appearance.

公开(公告)号：US6140161A

公开(公告)日：2000-10-31

申请号：US92001

申请日：1998-06-05

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/82 ,  H01L21/84 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L27/11807 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is a method for making a semiconductor integrated circuit device used to form a p-channel MOS field-effect transistor and a n-channel MOS field-effect transistor on a common SOI substrate with a structure that a first silicon layer, insulating film and a second silicon layer are layered;wherein the steps from sectioning a SOI layer as the second silicon layer by insulation separation into a plurality of active regions to forming at least one gate electrode to be laid through gate insulating film on the surface of each of the plurality of active regions are conducted with no relation to the conductivity type of MOS field-effect transistor.

摘要翻译： 公开了一种制造用于在公共SOI衬底上形成p沟道MOS场效应晶体管和n沟道MOS场效应晶体管的半导体集成电路器件的方法，其结构为：第一硅层，绝缘膜和 层叠第二硅层; 其中通过绝缘分离将SOI层作为第二硅层分离成多个有源区域以形成要在多个有源区域中的每一个的表面上铺设通过栅极绝缘膜的至少一个栅电极的步骤是用 与MOS场效应晶体管的导电类型无关。

公开(公告)号：US06719114B2

公开(公告)日：2004-04-13

申请号：US10226311

申请日：2002-08-23

申请人： Kouichi Kumagai ,  Takashi Kodama

发明人： Kouichi Kumagai ,  Takashi Kodama

IPC分类号： F16D1358

CPC分类号： F16D13/62

摘要： A clutch outer includes a cylindrical portion with a plurality of slits defined therein which extend in an axial direction of the cylindrical portion. Engagement claws on outer peripheries of a plurality of friction plates slidably engage the slits. Each slit includes a wide portion defined on an inner periphery of the cylindrical portion and into which the engagement claws are engaged, and a narrow portion defined on an outer periphery of the cylindrical portion with a width in a circumferential direction of the cylindrical portion being smaller than that of the wide portion. The wide and narrow portions are connected through a step facing a radially inward direction of the cylindrical portion. A draft for the wide portion during die-casting is less than a draft for the narrow portion, and a die-parting face in the die-casting is established on the side of the outer periphery of the cylindrical portion.

摘要翻译： 离合器外部包括圆筒形部分，其中限定有多个狭缝，其沿圆柱形部分的轴向方向延伸。 多个摩擦片的外周上的接合爪可滑动地接合狭缝。 每个狭缝包括限定在圆柱形部分的内周上并且接合爪接合的宽部分，并且限定在圆柱形部分的外圆周上的窄部分在圆柱形部分的圆周方向上的宽度较小 比广泛的部分。 宽和窄部分通过面向圆柱形部分的径向向内方向的台阶连接。 在压铸过程中宽幅部分的牵伸力小于狭窄部分的牵伸力，并且在圆筒部分的外周侧形成压铸件中的模切面。

公开(公告)号：US06643840B2

公开(公告)日：2003-11-04

申请号：US09775590

申请日：2001-02-05

申请人： Kouichi Kumagai

发明人： Kouichi Kumagai

IPC分类号： G06F1750

CPC分类号： G06F17/50

摘要： A designing method of a semiconductor integrated circuit is composed of providing a library storing a macro mask pattern for a macro circuit including buffer circuits, selecting one of the buffer circuits as a selected buffer circuit and arranging the macro mask pattern and a third wiring pattern to produce an integrated circuit mask. Each of buffer circuits is composed of first and second wirings apart from each other, a firs semiconductor element selectively supplying the first wiring with a power supply potential in accordance with the output signal and a second semiconductor element selectively supplying the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring. In the integrated circuit mask pattern, the first and second wiring patterns of the selected buffer circuit are connected with each other by the third wiring pattern.

摘要翻译： 半导体集成电路的设计方法包括：提供存储宏缓冲电路的宏观掩模图案的库，包括缓冲电路，选择缓冲电路之一作为选择的缓冲电路，并将宏观掩模图案和第三布线图案布置到 生成集成电路面罩。 每个缓冲电路由彼此分开的第一和第二布线组成，第一半导体元件根据输出信号选择性地向第一布线提供电源电位，第二半导体元件选择性地向第二布线提供接地电位 按照输出信号。 宏掩模图案包括缓冲器掩模图案，每个缓冲器掩模图案对应于缓冲器电路之一。 每个缓冲掩模图案由用于第一布线的第一布线图形和第二布线的第二布线图形组成。 在集成电路掩模图案中，所选择的缓冲电路的第一和第二布线图案通过第三布线图形相互连接。