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    Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude
    1.
    发明授权
    Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude 失效
    具有锁存电路的锁存电路和半导体集成电路具有电压振幅较大的控制信号

    公开(公告)号：US06404254B2

    公开(公告)日：2002-06-11

    申请号：US09166585

    申请日：1998-10-06

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

    IPC分类号： H03K3286

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356173

    摘要： A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side. In addition, the control signals are very few, and a fine timing control for changing over the mode is no longer required.

    摘要翻译： 一种半导体集成电路，其被配置为在备用模式中停止向逻辑电路供电，从而实现低功耗，包括锁存电路，其特征在于，作为控制信号，时钟信号在主动 模式，并且在备用模式下提供用于创建信息保持条件的信号，并且施加控制信号的MOSFET包括具有高阈值的第一导电型MOSFET和具有低阈值的第二导电类型MOSFET， 控制信号的幅度大于电源电压。 可以实现半导体集成电路，即主动模式中的高速操作和待机模式中的低功耗彼此兼容，并且如果用于逻辑电路的电源开关仅插入到 高电平电源电压侧和低电平电源电压线一侧。 此外，控制信号非常少，并且不再需要用于改变模式的精细定时控制。

    Latch type sense amplifier circuit
    2.
    发明授权
    Latch type sense amplifier circuit 有权
    锁存型读出放大器电路

    公开(公告)号：US06255862B1

    公开(公告)日：2001-07-03

    申请号：US09502231

    申请日：2000-02-11

    申请人： Kouichi Kumagai ,  Hiroaki Iwaki

    发明人： Kouichi Kumagai ,  Hiroaki Iwaki

    IPC分类号： H03F345

    CPC分类号： G11C7/065

    摘要： A latch type sense amplifier circuit comprises first and second latch circuits which output the same output signals when a potential difference between a bit line pair is equal to or greater than a predetermined value. The first and second latch circuits output different output signals when the potential difference between the bit line pair is less than the predetermined value. The latch type sense amplifier circuit further comprises a comparison result signal generating circuit which compares the output signals from the first and second latch circuits and outputs a signal indicative of the comparison result.

    摘要翻译： 锁存型读出放大器电路包括当位线对之间的电位差等于或大于预定值时输出相同输出信号的第一和第二锁存电路。 当位线对之间的电位差小于预定值时，第一和第二锁存电路输出不同的输出信号。 锁存型读出放大器电路还包括比较结果信号发生电路，其比较来自第一和第二锁存电路的输出信号，并输出指示比较结果的信号。

    Semiconductor integrated circuit having a sleep mode with low power and small area
    3.
    发明授权
    Semiconductor integrated circuit having a sleep mode with low power and small area 有权
    具有低功率和小面积的睡眠模式的半导体集成电路

    公开(公告)号：US06208170B1

    公开(公告)日：2001-03-27

    申请号：US09286029

    申请日：1999-04-05

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai

    IPC分类号： H03K19094

    CPC分类号： G11C5/14

    摘要： A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

    摘要翻译： 半导体集成电路包括具有全局源极线VCC，源极开关晶体管耦合到VCC的局部源极线QVCC和全局接地线VSS，低阈值逻辑（组合）电路的电源电路，其连接在QVCC和 VSS和连接在VCC和VSS之间的数据存储（顺序）电路。 数据存储电路包括用于从逻辑电路接收数据的低阈值输入部分和用于锁存由输入部分接收的数据的高阈值锁存部分。 模式开关晶体管插入在低阈值逻辑电路和VSS之间，低阈值输入部分和VCC之间以及低阈值输入部分和VSS之间，用于实现半导体集成电路的睡眠模式。 降低电路规模可以保持低功耗。

    Semiconductor memory device with several access enabled using single port memory cell
    4.
    发明授权
    Semiconductor memory device with several access enabled using single port memory cell 有权
    具有多路访问功能的半导体存储器件使用单端口存储单元

    公开(公告)号：US6134154A

    公开(公告)日：2000-10-17

    申请号：US281215

    申请日：1999-03-30

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai

    IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C8/16 ,  G11C11/419

    摘要： In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a plurality of word lines and is connected to one of a plurality of bit lines such that a plurality of columns are formed from the plurality of memory cells. A word line selecting section selects one of the plurality of word lines based on a first address. A first column selector selects one of the plurality of columns as a first column based on the first address. A second column selector selects another one of the plurality of columns as a second column based on a second address. An address data of a predetermined portion of the first address is not equal to an address data of the second address. An input/output section includes a first sense amplifier and a first buffer. A first read operation is performed to a first memory cell connected to the selected word line and the first column through the first sense amplifier and the first column selector and a first write operation is performed to a second memory cell connected to the selected word line and the second column through the first buffer and the second column selector.

    摘要翻译： 在半导体存储器件中，多个存储单元被布置成矩阵。 多个存储单元中的每一个连接到多个字线中的一个，并且连接到多个位线中的一个，使得从多个存储单元形成多个列。 字线选择部分基于第一地址来选择多个字线之一。 第一列选择器基于第一地址选择多个列之一作为第一列。 第二列选择器基于第二地址选择多个列中的另一列作为第二列。 第一地址的预定部分的地址数据不等于第二地址的地址数据。 输入/输出部分包括第一读出放大器和第一缓冲器。 通过第一读出放大器和第一列选择器对连接到所选字线和第一列的第一存储单元执行第一读操作，并且对连接到所选字线的第二存储单元执行第一写操作，并且 第二列通过第一缓冲区和第二列选择器。

    Low dissipation inverter circuit
    5.
    发明授权
    Low dissipation inverter circuit 失效
    低功耗逆变电路

    公开(公告)号：US06100720A

    公开(公告)日：2000-08-08

    申请号：US287582

    申请日：1999-04-06

    申请人： Kouichi Kumagai ,  Hiroaki Iwaki

    发明人： Kouichi Kumagai ,  Hiroaki Iwaki

    IPC分类号： H03K17/693 ,  H03K5/151 ,  H03K19/00 ,  H03K19/0948

    CPC分类号： H03K19/0019 ,  H03K5/151

    摘要： An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

    摘要翻译： 逆变器电路具有用于接收互补输入信号的第一和第二输入端子，用于输出从互补输入信号产生的互补输出信号的第一和第二输出端子，以及一对整流器部分， 输出端子的电位侧到输出端子的较低电位，以节省功耗。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5998879A

    公开(公告)日：1999-12-07

    申请号：US17960

    申请日：1998-02-03

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai

    IPC分类号： H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12

    CPC分类号： H01L27/1108 ,  H01L27/1203

    摘要： In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of the drain and source diffusion layer regions of the first and second MOS transistors are respectively arranged to be adgacent to each other and are electrically connected to each other, respectively, through a diffusion layer interconnection.

    摘要翻译： 在形成在SOI衬底上并包括具有第一和第二NMOS和PMOS晶体管的触发器的CMOS SRAM单元中，具有第一和第二MOS晶体管的传输门和字线部分，其特征在于：字线部分沿着 预定方向; 第一和第二NMOS和PMOS晶体管的源极和漏极扩散层区域沿着预定方向排列，并且这些NMOS和PMOS晶体管的栅极在垂直于预定方向的方向上布置在沟道区域上; 第一和第二NMOS晶体管的栅极分别电连接到第一和第二PMOS晶体管的栅极; 并且在沟道区上的第一和第二NMOS晶体管的栅极和沟道区上的第一和第二PMOS晶体管的栅极之间的区域中，fisrt和第二NMOS和PMOS晶体管的漏极扩散层区域中的每一个， 并且第一和第二MOS晶体管的漏极和源极扩散层区域中的每一个分别布置成彼此相邻并且分别通过扩散层互连彼此电连接。

    Semiconductor memory device that can relief defective address
    7.
    发明申请
    Semiconductor memory device that can relief defective address 审中-公开
    可以缓解缺陷地址的半导体存储器件

    公开(公告)号：US20100157704A1

    公开(公告)日：2010-06-24

    申请号：US12654285

    申请日：2009-12-16

    申请人： Hiroaki Iwaki

    发明人： Hiroaki Iwaki

    IPC分类号： G11C29/00 ,  G11C8/00 ,  G11C17/16

    CPC分类号： G11C17/165 ,  G11C29/84

    摘要： Plural nonvolatile address storing circuits hold address data. A serial transfer circuit sequentially transfers the address data stored in each of the nonvolatile address storing circuits. A serial reception circuit sequentially receives the address data transferred by the serial transfer circuit. An address latch circuit holds the address data received by the serial reception circuit. An address comparison circuit compares each of the address data stored in the address latch circuit with an input address, and determines whether each address data coincides with the input address.

    摘要翻译： 多个非易失性地址存储电路保存地址数据。 串行传送电路顺序传送存储在每个非易失性地址存储电路中的地址数据。 串行接收电路顺序地接收由串行传送电路传送的地址数据。 地址锁存电路保存串行接收电路所接收的地址数据。 地址比较电路将存储在地址锁存电路中的每个地址数据与输入地址进行比较，并确定每个地址数据是否与输入地址一致。

    Address generating circuit and semiconductor memory device
    8.
    发明申请
    Address generating circuit and semiconductor memory device 审中-公开
    地址发生电路和半导体存储器件

    公开(公告)号：US20090138537A1

    公开(公告)日：2009-05-28

    申请号：US12292257

    申请日：2008-11-14

    申请人： Hiroaki Iwaki

    发明人： Hiroaki Iwaki

    IPC分类号： G06F7/50

    CPC分类号： G06F7/507

    摘要： An address generating circuit includes a first carry look-ahead circuit for performing an operation using an inputted first carry and a first address and outputting a first output address and a first output carry respectively as a first operation result, a second carry look-ahead circuit for performing an operation using a carry fixed to 0 and a second address and outputting a second output address and a second output carry respectively as a second operation result, a third carry look-ahead circuit for performing an operation using a carry fixed to 1 and the second address and outputting a third output address and a third output carry respectively as a third operation result, and a first select circuit for selecting either of the second and third operation results based on the first output carry and outputting the selected operation result.

    摘要翻译： 地址发生电路包括：第一进位查找电路，用于执行使用输入的第一进位和第一地址的操作，并分别输出第一输出地址和第一输出进位作为第一运算结果;第二进位查找电路 用于执行使用进位固定为0和第二地址的操作，并分别输出第二输出地址和第二输出进位作为第二运算结果;第三进位查询电路，用于执行使用固定为1的运算和 所述第二地址分别输出第三输出地址和第三输出进位作为第三运算结果;以及第一选择电路，用于基于所述第一输出进位选择所述第二运算结果和所述运算结果中的任一个，并输出所选择的运算结果。

    Recombinant cyclopentanone monooxygenase [cpmo]
    10.
    发明授权
    Recombinant cyclopentanone monooxygenase [cpmo] 失效
    重组环戊酮单加氧酶[cpmo]

    公开(公告)号：US07541168B2

    公开(公告)日：2009-06-02

    申请号：US11727730

    申请日：2007-03-28

    申请人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    发明人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    IPC分类号： C12N9/02 ,  C07H21/04

    CPC分类号： C12N9/0073 ,  C12Y114/13016

    摘要： Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mr, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

    摘要翻译： 来自Comamonas（以前为假单胞菌）的环戊酮1,2-单加氧酶（CPMO） 菌株NCIMB 9872进行降解途径的第二步，其允许细菌使用环戊醇作为生长的唯一碳源。 在本发明中，报道了CPMO编码基因（cpnB）在4.3kb SphI片段上的定位，确定其序列。 发现由该基因编码的550个氨基酸的CPMO多肽（Mr，62,111）与不动杆菌属的环己酮1,2-单加氧酶（CHMO）的序列具有36.5％的同一性。 菌株NCIMB 9871.62-kDa CPMO在大肠杆菌中表达为IPTG诱导蛋白。