公开(公告)号：US20070052852A1

公开(公告)日：2007-03-08

申请号：US11513354

申请日：2006-08-31

申请人： Keisuke Yorioka ,  Yoshihiro Nakahara ,  Kouji Nakajima ,  Manabu Kuroda

发明人： Keisuke Yorioka ,  Yoshihiro Nakahara ,  Kouji Nakajima ,  Manabu Kuroda

IPC分类号： H04N5/46 ,  H04N9/64

CPC分类号： G09G5/393 ,  G09G5/18 ,  G09G5/395 ,  G09G2320/106 ,  H04N7/0122

摘要： An address generating unit 102 generates a different write start address (w_adr) of a picture memory 105 depending on an aspect ratio and/or a display plane position of a motion picture to be displayed. A picture writing unit 104 writes data to the picture memory 105, starting at the calculated write start address (w_adr). A picture reading unit 108 uses the write start address (w_adr) as a read start address (r_adr) and reads data from the picture memory 105, starting at the read start address (r_adr).

摘要翻译： 地址生成单元102根据要显示的运动图像的宽高比和/或显示平面位置生成图片存储器105的不同的写入开始地址（w_adr）。 图像写入单元104从计算出的写开始地址（w_adr）开始将数据写入图像存储器105。 图像读取单元108使用写开始地址（w_adr）作为读取开始地址（r_adr），并从读取的起始地址（r_adr）开始从图片存储器105读取数据。

公开(公告)号：US20050182916A1

公开(公告)日：2005-08-18

申请号：US10949230

申请日：2004-09-27

申请人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

发明人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3885

摘要： A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

摘要翻译： 提供了具有指令集的VLIW处理器，其大小被减小以便需要少量位来指定寄存器。 VLIW处理器10包括寄存器文件12，第一个第三操作单元14 a-14 c等，并且执行非常长的指令字。 并且，长指令字包括指定寄存器文件12中的至少一个寄存器的寄存器指定字段和多个指令。 每个指令的操作数都有位src 1 src 2和dst，表示由寄存器指定字段指定的寄存器是否用作源寄存器和目的寄存器。

公开(公告)号：US06919771B2

公开(公告)日：2005-07-19

申请号：US10669374

申请日：2003-09-25

申请人： Kouji Nakajima

发明人： Kouji Nakajima

IPC分类号： H03F3/181 ,  H03F3/217 ,  H03F3/38 ,  H03G3/30 ,  H03G3/34 ,  H03K7/08 ,  G11B20/10

CPC分类号： H03G3/3021 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/351 ,  H03G3/341

摘要： An object of the present invention is to provide a digital amplifier which is capable of preventing a reproduction of an analogue audio signal from a loud speaker, when an output sound volume from the loud speaker is set to zero and when inputting of a digital audio signal or an input signal is stopped. In order to achieve the object, in the digital amplifier of the present invention, a silent PWM signal output section 7 outputs a PWM signal having a duty ratio of 50%, instead of a PWM signal generated by the PWM signal generating section 6, in the following cases: the factor detecting section 3 detects that the digital audio signal is multiplied by the factor “0” in the gain regulation section 2, the silent signal determining section 4 determines that the signal input from the reproducing unit 13 is stopped, and the silent signal determining section 4 determines that the digital audio signal is a signal at a silent level.

摘要翻译： 本发明的目的是提供一种数字放大器，其能够防止从扬声器再现模拟音频信号，当来自扬声器的输出音量被设置为零时，并且当输入数字音频信号 或输入信号停止。 为了实现该目的，在本发明的数字放大器中，静音PWM信号输出部分7输出占空比为50％的PWM信号，而不是由PWM信号产生部分6产生的PWM信号 以下情况：因素检测部分3检测到数字音频信号在增益调节部分2中乘以因子“0”，无声信号确定部分4确定从再现单元13输入的信号停止，以及 无声信号确定部分4确定数字音频信号是静音级的信号。

公开(公告)号：US06211610B1

公开(公告)日：2001-04-03

申请号：US09115651

申请日：1998-07-15

申请人： Kouji Nakajima

发明人： Kouji Nakajima

IPC分类号： H01J2976

CPC分类号： H01J29/703

摘要： A cathode ray tube including (a) a panel having a fluorescent film on an inner surface thereof for three primary colors emission, (b) an electron gun for emitting electron beams to the fluorescent film, (c) a deflecting yoke located between the panel and the electron gun, and including first and second coils for generating horizontally and vertically deflected magnet fields, (d) at least one first compensator (34) composed of magnetic substance having high magnetic permeability and low hysteresis characteristic for compensating for a profile of magnetic flux density in the horizontally deflected magnetic field, and (e) at least one second compensator (35) composed of magnetic substance having hysteresis characteristic for keeping magnetization when a polarity of the horizontally deflected magnetic field is inverted. The first compensator compensates for misconvergence generated between a central electron beam and two electron beams between which the central electron beam is situated, and the second compensator compensates for misconvergence generated between the two electron beams. Thus, misconvergence is readily compensated for, ensuring qualified images on a screen.

摘要翻译： 一种阴极射线管，包括：（a）在其内表面具有用于三原色发射的荧光膜的面板，（b）用于向荧光膜发射电子束的电子枪，（c）位于面板之间的偏转磁轭 和电子枪，并且包括用于产生水平和垂直偏转的磁场的第一和第二线圈，（d）由具有高导磁率和低磁滞特性的磁性物质组成的至少一个第一补偿器（34），用于补偿磁场的轮廓 水平偏转磁场中的磁通密度;（e）至少一个第二补偿器（35），其由具有磁滞特性的磁性体组成，该磁滞特性用于当水平偏转磁场的极性反转时保持磁化。 第一补偿器补偿在中心电子束和中心电子束所在的两个电子束之间产生的失会聚，第二补偿器补偿在两个电子束之间产生的失会聚。 因此，容易地弥补失会聚，从而确保屏幕上的合格图像。

公开(公告)号：US08588304B2

公开(公告)日：2013-11-19

申请号：US11393426

申请日：2006-03-30

申请人： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

发明人： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

IPC分类号： H04N7/12

CPC分类号： H04N19/513 ,  H04N19/122 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/51 ,  H04N19/583 ,  H04N19/61 ,  H04N19/70

摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

摘要翻译： 通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。 视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够执行运动补偿操作。 视频解码装置复制分配给给定块的运动矢量以产生与给定块中的子块一样多的运动矢量，并且使用相应的重复运动矢量对每个子块执行运动补偿。 对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

公开(公告)号：US08183645B2

公开(公告)日：2012-05-22

申请号：US12588392

申请日：2009-10-14

申请人： Kouji Nakajima

发明人： Kouji Nakajima

IPC分类号： H01L21/70

CPC分类号： H01L29/7802 ,  H01L21/823475 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/7813

摘要： Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are arranged and a gate finger region different from a region where the cell region is formed. In the cell region, a gate electrode formed of a polysilicon (first conductive material) is formed. A polysilicon layer formed indivisibly with the gate electrode is formed in the gate finger region. An adhesion metal layer and a wiring metal layer are formed above the polysilicon layer by a lift-off method. The gate lead-out electrode is formed of a laminate structure including the polysilicon layer, the adhesion metal layer, and the wiring metal layer. A single layer of interlayer insulation film covering them is formed, on which a source electrode is formed.

摘要翻译： 在不增加半导体器件的芯片厚度的情况下，增强了栅极引出电极和源电极的图案布局设计的灵活性。 半导体器件包括布置多个晶体管单元的单元区域和与形成单元区域的区域不同的栅极指状区域。 在单元区域中，形成由多晶硅（第一导电材料）形成的栅电极。 在栅指区域中形成与栅电极不可分割地形成的多晶硅层。 通过剥离法在多晶硅层的上方形成粘附金属层和布线金属层。 栅极引出电极由包括多晶硅层，粘合金属层和布线金属层的层叠结构形成。 形成覆盖它们的单层层间绝缘膜，在其上形成源电极。

公开(公告)号：US20120087413A1

公开(公告)日：2012-04-12

申请号：US13328950

申请日：2011-12-16

申请人： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

发明人： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

IPC分类号： H04N7/36 ,  H04N7/26

CPC分类号： H04N19/513 ,  H04N19/122 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/51 ,  H04N19/583 ,  H04N19/61 ,  H04N19/70

摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

摘要翻译： 通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。 视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够执行运动补偿操作。 视频解码装置复制分配给给定块的运动矢量以产生与给定块中的子块一样多的运动矢量，并且使用相应的重复运动矢量对每个子块执行运动补偿。 对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

公开(公告)号：US08738892B2

公开(公告)日：2014-05-27

申请号：US12103372

申请日：2008-04-15

申请人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

发明人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

IPC分类号： G06F15/00

CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3885

摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

摘要翻译： 具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。 此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。 每个指令的操作数包括位src1，src2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

公开(公告)号：US20090268822A1

公开(公告)日：2009-10-29

申请号：US12273717

申请日：2008-11-19

申请人： Kengo TERADA ,  Kouji Nakajima ,  Keisuke Kondou

发明人： Kengo TERADA ,  Kouji Nakajima ,  Keisuke Kondou

IPC分类号： H04N11/02 ,  G06K9/36 ,  H04N7/12

CPC分类号： H04N19/533 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/61

摘要： A moving image encoding apparatus includes a motion vector detecting unit for executing from a wide and coarse search to a narrow and fine search in a plurality of steps and in a stepwise manner to detect a motion vector of each block in an input image. The motion vector detecting unit includes a block combining unit for generating a combination block, depending on a result of detection in a search step, a search use pixel extracting unit for extracting a search use pixel to be used in a next search step, from the combination block, and a second search combination block searching unit for performing the next search step with respect to the combination block using the search use pixel, and setting a detected motion vector of the combination block as the motion vector of each block of the combination block.

摘要翻译： 运动图像编码装置包括：运动矢量检测单元，用于从多个步骤中以逐步的方式从广泛粗略搜索到窄和精细搜索，以检测输入图像中每个块的运动矢量。 运动矢量检测单元包括：块组合单元，用于根据搜索步骤中的检测结果生成组合块;搜索使用像素提取单元，用于从下一个搜索步骤中提取要使用的搜索使用像素 组合块和第二搜索组合块搜索单元，用于使用搜索使用像素执行关于组合块的下一个搜索步骤，并且将检测到的组合块的运动矢量设置为组合块的每个块的运动矢量 。

公开(公告)号：US07383422B2

公开(公告)日：2008-06-03

申请号：US10949230

申请日：2004-09-27

申请人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

发明人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

IPC分类号： G06F15/76

CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3885

摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

摘要翻译： 具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。 此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。 每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。