公开(公告)号：US09023707B1

公开(公告)日：2015-05-05

申请号：US13312964

申请日：2011-12-06

申请人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC分类号： H01L21/336 ,  H01L21/768

CPC分类号： H01L21/768 ,  H01L27/11568 ,  H01L29/792

摘要： Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

摘要翻译： 提供了ONO集成到MOS流中的方法。 在一个实施例中，该方法包括：（i）在衬底的MOS器件区域的上方形成焊盘电介质层; 并且（ii）在衬底的非易失性器件区域之上形成图案化的电介质堆叠，所述图案化的电介质叠层包括隧道层，电荷俘获层和牺牲顶层，所述电荷俘获层包括多个层，包括 形成在隧道层上的第一氮化物层和第二氮化物层，其中第一氮化物层相对于第二氮化物层富氧。 还描述了其它实施例。

公开(公告)号：US08071453B1

公开(公告)日：2011-12-06

申请号：US12608886

申请日：2009-10-29

申请人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC分类号： H01L21/336

CPC分类号： H01L21/768 ,  H01L27/11568 ,  H01L29/792

摘要： A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.

摘要翻译： 描述了将非易失性存储器件（例如EEPROM，浮动栅极FLASH和SONOS）的ONO集成到基准MOS器件（例如MOSFET）中的方法。 在一个实施例中，在将沟道植入物形成MOS器件之前形成底部的两个ONO层，并且顶部ONO层与MOS器件的栅极氧化物同时形成。

公开(公告)号：US20090032863A1

公开(公告)日：2009-02-05

申请号：US12005813

申请日：2007-12-27

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

公开(公告)号：US20080290399A1

公开(公告)日：2008-11-27

申请号：US11904475

申请日：2007-09-26

申请人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

发明人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

摘要： A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

摘要翻译： 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US08679927B2

公开(公告)日：2014-03-25

申请号：US12185751

申请日：2008-08-04

申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC分类号： H01L29/792

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US08536640B2

公开(公告)日：2013-09-17

申请号：US11904474

申请日：2007-09-26

申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

摘要： A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

公开(公告)号：US08093128B2

公开(公告)日：2012-01-10

申请号：US12125864

申请日：2008-05-22

申请人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

发明人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC分类号： H01L29/792

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US20090020831A1

公开(公告)日：2009-01-22

申请号：US11904474

申请日：2007-09-26

申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

摘要： A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

摘要翻译： 具有充电阱的氘钝化的非挥发性电荷陷阱存储器件及其制造方法。 氘代栅极层，氘化栅极覆盖层和氘代间隔物被采用各种组合，以将器件与邻近栅极堆叠内的界面的氘源以及可能存在阱的栅极堆叠的表面封装。

公开(公告)号：US08680601B2

公开(公告)日：2014-03-25

申请号：US11904475

申请日：2007-09-26

申请人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

发明人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

摘要： A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

摘要翻译： 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US08637921B2

公开(公告)日：2014-01-28

申请号：US12005813

申请日：2007-12-27

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，所述方法包括氧化，氮化，再氧化和再纳入。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。