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53 条记录 (耗时 0.017 秒)

    SnSe-Based Limited Reprogrammable Cell
    1.
    发明申请
    SnSe-Based Limited Reprogrammable Cell 有权
    基于SnSe的有限可编程单元

    公开(公告)号：US20080067489A1

    公开(公告)日：2008-03-20

    申请号：US11943339

    申请日：2007-11-20

    申请人： Kristy Campbell

    发明人： Kristy Campbell

    IPC分类号： H01L29/04

    CPC分类号： H01L45/085 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/56 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

    摘要： Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a second electrode and a layer of a chalcogenide or germanium comprising material between the first electrode and the second electrode. The memory device further includes a tin-chalcogenide layer between the chalcogenide or germanium comprising material layer and the second electrode.

    摘要翻译： 用于提供可被编程有限次数的存储器件的方法和装置。 根据示例性实施例，存储器件及其形成方法在第一电极和第二电极之间提供第一电极，第二电极和包含硫族化物或锗的材料层。 记忆装置还包括在硫属化物或包含锗的材料层和第二电极之间的锡 - 硫族化物层。

    Phase change memory cell and method of formation
    3.
    发明申请
    Phase change memory cell and method of formation 有权
    相变记忆单元及其形成方法

    公开(公告)号：US20070029537A1

    公开(公告)日：2007-02-08

    申请号：US11194623

    申请日：2005-08-02

    申请人： Kristy Campbell

    发明人： Kristy Campbell

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1233 ,  H01L45/06 ,  H01L45/144

    摘要： A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second electrode is over the metal-chalcogenide layer. The memory element is configured to have reduced current requirements.

    摘要翻译： 提供了一种相变存储元件及其形成方法。 存储元件包括在第一电极上的包括相变材料层的第一电极和硫族化物。 金属硫族化物层位于相变材料层的上方。 金属硫族化物层是锡 - 碲化物。 第二电极在金属 - 硫族化物层之上。 存储器元件被配置为具有减小的电流要求。

    Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry
    4.
    发明申请
    Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry 有权
    形成非易失性电阻可变器件的方法和形成存储器电路的可编程存储器单元的方法

    公开(公告)号：US20060270099A1

    公开(公告)日：2006-11-30

    申请号：US11430046

    申请日：2006-05-09

    申请人： Kristy Campbell ,  John Moore

    发明人： Kristy Campbell ,  John Moore

    IPC分类号： H01L21/00

    CPC分类号： H01L45/1233 ,  H01L45/04 ,  H01L45/085 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1658 ,  H01L45/1683

    摘要： A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing,. a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.

    摘要翻译： 在基板上形成第一导电电极材料。 在其上形成包含硫属元素的材料。 硫族化物材料包含A x S y S y。 在硫族化物材料上形成含银层。 银被照射有效地破坏硫族化物材料在含银层和硫族化物材料的界面处的硫属化物键，并将至少一些银扩散到硫族化物材料中。 在照射之后，硫族化物材料外表面暴露于含有碘的流体，其有效地减少硫族化物材料外表面的暴露之前的粗糙度。 暴露后， 第二导电电极材料沉积在硫族化物材料上，其连续并完全覆盖至少在硫族化物材料上，并且第二导电电极材料形成为器件的电极。

    SnSe-based limited reprogrammable cell
    6.
    发明申请
    SnSe-based limited reprogrammable cell 有权
    基于SnSe的有限可编程单元

    公开(公告)号：US20060186394A1

    公开(公告)日：2006-08-24

    申请号：US11062436

    申请日：2005-02-23

    申请人： Kristy Campbell

    发明人： Kristy Campbell

    IPC分类号： H01L29/04

    CPC分类号： H01L45/085 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/56 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

    摘要： Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a second electrode and a layer of a chalcogenide or germanium comprising material between the first electrode and the second electrode. The memory device further includes a tin-chalcogenide layer between the chalcogenide or germanium comprising material layer and the second electrode.

    摘要翻译： 用于提供可被编程有限次数的存储器件的方法和装置。 根据示例性实施例，存储器件及其形成方法在第一电极和第二电极之间提供第一电极，第二电极和包含硫族化物或锗的材料层。 记忆装置还包括在硫属化物或包含锗的材料层和第二电极之间的锡 - 硫族化物层。

    Assemblies displaying differential negative resistance
    8.
    发明申请
    Assemblies displaying differential negative resistance 审中-公开
    显示差分负电阻的组件

    公开(公告)号：US20050247927A1

    公开(公告)日：2005-11-10

    申请号：US11180692

    申请日：2005-07-14

    申请人： Kristy Campbell

    发明人： Kristy Campbell

    IPC分类号： H01L29/267 ,  H01L29/88 ,  H01L47/00 ,  H01L29/06

    CPC分类号： H01L47/005 ,  H01L29/267 ,  H01L29/88 ,  H01L47/00

    摘要： The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of S, Te and Se. A second layer is over the first layer. The second layer comprises M and A, where M is a transition metal and A is one or more of O, S, Te and Se. A third layer is over the second layer, and comprises Ge and one or more of S, Te and Se. The first, second and third layers are together incorporated into an assembly displaying differential negative resistance. Additionally, the invention includes methodology for forming assemblies displaying differential negative resistance, such as tunnel diode assemblies.

    摘要翻译： 本发明包括显示差分负电阻的器件，其特征在于具有至少约9的峰谷比的电流对电压分布。本发明还包括半导体结构，其包括衬底和衬底上的第一层 。 第一层包括Ge和S，Te和Se中的一种或多种。 第二层在第一层之上。 第二层包括M和A，其中M是过渡金属，A是O，S，Te和Se中的一种或多种。 第三层在第二层之上，并且包括Ge和S，Te和Se中的一种或多种。 第一，第二和第三层一起并入显示差分负电阻的组件中。 此外，本发明包括形成显示差分负电阻的组件的方法，例如隧道二极管组件。

    Method of refreshing a PCRAM memory device
    9.
    发明申请
    Method of refreshing a PCRAM memory device 有权

    公开(公告)号：US20050007852A1

    公开(公告)日：2005-01-13

    申请号：US10614160

    申请日：2003-07-08

    申请人： John Moore ,  Terry Gilton ,  Kristy Campbell

    发明人： John Moore ,  Terry Gilton ,  Kristy Campbell

    IPC分类号： G11C11/406 ,  G11C13/02 ,  G11C16/02 ,  G11C7/00

    CPC分类号： G11C13/0069 ,  G11C11/406 ,  G11C11/40622 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0033 ,  G11C16/3431 ,  G11C2211/4065 ,  G11C2211/4068 ,  G11C2213/79

    摘要： A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of discrete refresh voltages to the PCRAM cells in an array. Specifically, the array structure of a PCRAM device is constructed to allow leakage current to flow through each programmed cell in the array to refresh the programmed state. In one embodiment, the leakage current flows across the access device between the anode of the memory element and the bit line to which the cell is connected, for each memory cell in the array which has been programmed to the low resistance state. In another embodiment, the leakage current flows to the programmed cells through a doped substrate or doped regions of a substrate on which each cell is formed. An entire array is refreshed simultaneously by forming each memory element in the array to have one common anode formed as a single cell plate for the array. Only PCRAM cells in the array written to the low resistance state are refreshed by the controlled leakage current, whereas cells in the high resistance state are not affected by the refresh operation.